DFT Senior Engineer

HCLTech; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

HCLTech in Bengaluru is seeking an experienced DFT Engineer with 9+ years in ASIC/SoC design for DFT implementation and validation. You will architect, implement, and verify DFT solutions for complex SoCs.

Collaborate with RTL, Verification, Physical Design, and Product Engineering teams to ensure DFT sign-off and tape-out readiness, develop DFT flows, and support post-silicon testing.

Qualifications

• 9+ years of hands-on DFT experience.
• Strong expertise in DFT methods and verification.
• Experience with SoC-level DFT integration and DRC/debug.

Responsibilities

• Define and implement DFT architecture for complex SoCs.
• Integrate and verify Scan, MBIST, Boundary Scan (JTAG), and compression logic.
• Perform DFT rule checks, ATPG pattern generation, and pattern validation.
• Analyze test coverage, debug coverage issues, and drive closure.
• Develop and maintain DFT flows, scripts, and automation.
• Support post-silicon bring-up and production testing activities.
• Work closely with RTL, Verification, Physical Design, and Product Engineering teams.
• Ensure successful DFT sign-off and tape-out readiness.

Skills

Scan Insertion

Scan Compression

ATPG & Fault Coverage

MBIST Implementation

JTAG 1149.1

DFT DRC & Debug

SoC DFT Integration

Education

B.E./B.Tech/M.E./M.Tech in Electronics or related disciplines

Job description

Looking for an experienced DFT Engineer with 9+ years of industry experience in ASIC/SoC Design for Test (DFT) implementation and validation. The candidate will be responsible for architecting, implementing, and verifying DFT solutions for complex SoCs.

Key Responsibilities

• Define and implement DFT architecture for complex SoCs.
• Integrate and verify Scan, MBIST, Boundary Scan (JTAG), and compression logic.
• Perform DFT rule checks, ATPG pattern generation, and pattern validation.
• Analyze test coverage, debug coverage issues, and drive closure.
• Develop and maintain DFT flows, scripts, and automation.
• Support post-silicon bring-up and production testing activities.
• Work closely with RTL, Verification, Physical Design, and Product Engineering teams.
• Ensure successful DFT sign-off and tape-out readiness.

Mandatory Skills

9+ years of hands-on DFT experience

Strong expertise in:

• Scan Insertion and Scan Compression
• ATPG and Fault Coverage Analysis
• MBIST Implementation and Verification
• JTAG / IEEE 1149.1
• DFT DRC and Debug
• SoC-level DFT Integration

Educational Qualification

• B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related disciplines.