Hiring For DFT Lead / DFT Practice Head

Mirafra; Hyderabad, Bengaluru, Delhi; On-site; INR 6,000,000 - 9,000,000; Full time

Job summary

Mirafra is seeking an experienced DFT Lead in India to drive design for testability for complex ASIC/SoC designs. The role requires hands-on DFT architecture, scan insertion, ATPG, and test coverage improvements across RTL-to-GDSII flows.

The candidate will lead DFT planning, sign-off, and coordination with RTL, verification, physical design, and silicon test teams. 7+ years of relevant experience is expected.

Qualifications

• 7+ years of DFT experience in ASIC/SoC environments.
• Strong DFT concepts, scan insertion, ATPG, and test coverage optimization.
• Familiarity with RTL-to-GDSII flows and cross-functional teams.

Responsibilities

• Lead DFT architecture, planning, implementation, and sign-off for ASIC/SoC designs.
• Drive scan insertion, scan compression, scan chain optimization, and ATPG patterns.
• Own DFT rules checking (DRC), fault coverage analysis, and test improvements.
• Lead MBIST, memory test methods, JTAG/boundary scan, and 1149.x implementations.
• Work on stuck-at, transition-delay, and other fault models.
• Integrate DFT across synthesis, physical design, and gate-level sim.
• Collaborate with RTL, verification, physical design, STA, and silicon test teams.
• Drive DFT timing, area, routing, and testability optimization.
• Review deliverables, mentor engineers, and ensure project milestones.

Tools

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Job description

Job Title: DFT Lead

Experience: 7+ Years
Location: Bengaluru / Hyderabad / Noida
Job Type: Full-time

Job Summary

We are looking for an experienced DFT Lead to drive Design for Testability activities for complex ASIC/SoC designs. The candidate should have strong hands-on experience in DFT architecture, scan insertion, ATPG, test coverage improvement, and DFT implementation across the RTL-to-GDSII flow.

Key Responsibilities

• Lead DFT architecture, planning, implementation, and sign-off for ASIC/SoC designs.
• Drive scan insertion, scan compression, scan chain optimization, and ATPG pattern generation.
• Own DFT rule checking (DRC), fault coverage analysis, and test coverage improvement.
• Lead MBIST, memory repair, JTAG, boundary scan, and IEEE 1149.1/1500/1687 implementation, as applicable.
• Work on stuck-at, transition-delay, and other relevant fault models.
• Perform DFT integration and debug issues across synthesis, physical design, and gate-level simulation.
• Collaborate with RTL, verification, physical design, STA, and silicon test teams.
• Drive DFT timing, area, routing, and testability optimization.
• Review technical deliverables, mentor junior engineers, and provide technical guidance to the team.
• Own DFT quality, project milestones, and sign-off deliverables.

Required Technical Skills

• Strong expertise in DFT concepts and ASIC/SoC design flows.
• Hands-on experience with scan insertion, ATPG, scan compression, and DFT DRC.
• Experience with tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
• Good knowledge of Verilog/SystemVerilog, Tcl, and scripting.
• Experience with MBIST, JTAG, boundary scan, and memory test methodologies.
• Understanding of fault models, test coverage, pattern validation, and DFT sign-off.
• Experience working with RTL-to-GDSII flows and cross-functional design teams.