DFT Engineer

Incise Infotech Pvt. Ltd.; Chennai District; On-site; INR 800,000 - 1,200,000; Full time

Benefits offered by this job

Opportunity to work on cutting-edge semiconductor technologies

Collaborative work environment

Competitive salary

Job summary

Incise Infotech Pvt. Ltd. is seeking a skilled DFT (Design for Testability) Engineer in Chennai, India, with 3–5 years of experience in ASIC/SoC design. The successful candidate will focus on DFT architecture development, scan insertion, and collaborating with engineering teams to ensure DFT readiness.

Ideal candidates should hold a degree in Electronics/Electrical Engineering and have hands-on expertise with industry-standard DFT tools. The role offers a competitive salary and opportunities for growth.

Qualifications

• 3–5 years of hands-on experience in DFT engineering.
• Strong knowledge of scan compression and JTAG.
• Experience in debugging DFT and silicon bring-up.

Responsibilities

• Develop and implement DFT architectures for ASIC/SoC designs.
• Perform scan insertion and fault coverage analysis.
• Collaborate with RTL and Physical Design teams.

Skills

DFT engineering expertise

Scan architecture knowledge

ATPG methodologies

Problem-solving skills

Education

Bachelor’s/Master’s degree in Electronics/Electrical Engineering

Tools

Synopsys DFT Compiler

Cadence Modus

Mentor Tessent

Job description

Job Description

We are looking for a skilled and motivated DFT (Design for Testability) Engineer with 3–5 years of experience in ASIC/SoC design and verification. The ideal candidate should have hands‑on expertise in DFT implementation, scan insertion, ATPG, and debugging activities for complex semiconductor designs.

Key Responsibilities

• Develop and implement DFT architectures for ASIC/SoC designs.
• Perform scan insertion, ATPG generation, and fault coverage analysis.
• Work on MBIST/LBIST implementation and validation.
• Collaborate with RTL, Physical Design, and Verification teams to ensure DFT readiness.
• Analyze and debug scan chain, pattern, and silicon‑related issues.
• Support post‑silicon validation and production testing activities.
• Ensure test coverage targets and quality metrics are achieved.
• Create and maintain DFT documentation and reports.

Required Skills & Qualifications

• Bachelor’s/Master’s degree in Electronics/Electrical Engineering or related field.
• 3–5 years of hands‑on experience in DFT engineering.
• Strong knowledge of scan architecture and scan compression, ATPG methodologies, MBIST/LBIST concepts, JTAG/Boundary Scan, fault models and test coverage analysis.
• Experience with industry‑standard tools such as Synopsys DFT Compiler / Tetramax / TestMAX, Cadence Modus, Mentor Tessent.
• Good understanding of RTL design, Verilog/SystemVerilog, and ASIC design flow.
• Experience in debugging DFT and silicon bring‑up issues.
• Strong analytical and problem‑solving skills.

Preferred Skills

• Experience with low‑power DFT techniques.
• Knowledge of scripting languages like Perl, Tcl, or Python.
• Exposure to STA and physical design constraints related to DFT.
• Good communication and teamwork skills.

What We Offer

• Opportunity to work on cutting‑edge semiconductor technologies.
• Collaborative and innovation‑driven work environment.
• Competitive salary and growth opportunities.

Those interested can share resume at [e-mail]