DFT Design Engineer - ASIC/SoC

Sykatiya Technologies Pvt Ltd; Hyderabad; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Sykatiya Technologies Pvt Ltd in India is seeking an experienced DFT Engineer to join our ASIC/SoC design team in Bangalore/Hyderabad. You will implement DFT, ATPG, and test architecture across complex designs.

The role collaborates with RTL, Physical Design, Verification and Product Engineering to boost test quality, coverage, and optimize silicon test. We value hands-on execution and strong problem solving to drive robust test solutions.

Qualifications

• Hands-on experience in DFT for ASIC/SoC designs.
• Proficient in ATPG pattern generation and simulations.
• Knowledge of MBIST, scan insertion, and test architecture.
• Experience with JTAG and boundary scan techniques.

Responsibilities

• Develop and implement DFT strategies for ASIC/SoC designs.
• Perform MBIST planning, architecture definition, and insertion.
• Execute scan architecture planning, scan insertion, and chain configuration.
• Implement test compression and wrapper insertion for efficiency.
• Generate ATPG patterns and run simulations and validation.
• Work on flat and hierarchical SoC designs ensuring integration.
• Collaborate with RTL, Physical Design, and Verification teams on DFT issues.
• Create STA constraints for DFT modes including shift, capture, and test operations.
• Analyze DFT rule checks and resolve testability issues.
• Assist with post-silicon testing and silicon bring-up.

Skills

DFT implementation

ATPG patterns

MBIST

Scan insertion

Wrapper insertion

JTAG boundary scan

STA constraints

Hierarchical SoC

Job description

Job Title :

DFT Engineer

Experience :

3 - 8 Years

Location :

Bangalore / Hyderabad

About The Role

We are seeking skilled Design for Testability (DFT) Engineers to join our ASIC/SoC design team. The ideal candidate will have hands‑on experience in DFT implementation, ATPG pattern generation, and test architecture development for complex SoC designs. The role involves collaborating with RTL Design, Physical Design, Verification, and Product Engineering teams to ensure high test coverage, improved test quality, and efficient silicon testing.

Key Responsibilities

• Develop and implement DFT strategies for complex ASIC/SoC designs.
• Perform MBIST planning, architecture definition, and insertion.
• Execute scan architecture planning, scan insertion, and scan‑chain configuration.
• Implement test compression and wrapper insertion for improved test efficiency.
• Generate ATPG patterns and perform ATPG simulations and pattern validation.
• Handle both flat and hierarchical SoC designs, ensuring effective DFT integration.
• Work on JTAG implementation, IEEE 1149.1, and boundary scan architecture.
• Create and validate STA constraints for various DFT modes, including shift, capture, and test operations.
• Analyze DFT rule‑checking (DRC) violations and resolve testability issues.
• Collaborate with RTL, Physical Design, and Verification teams to resolve DFT‑related issues.
• Support timing, coverage, and test‑quality optimization throughout the design cycle.
• Assist with post‑silicon testing, silicon bring‑up, and debugging of DFT‑related issues.

Required Skills

• 3 - 8 years of hands‑on experience in DFT implementation and ATPG activities.
• Strong knowledge of MBIST, scan insertion, scan compression, and wrapper insertion.
• Experience in ATPG pattern generation, simulation, and fault coverage analysis.
• Proficiency in handling flat and hierarchical SoC designs.
• Good understanding of JTAG, boundary scan, and DFT architecture.
• Experience in creating STA constraints for DFT modes.
• Knowledge of DFT rule checks, scan‑chain debugging, and test coverage improvement.
• Familiarity with industry‑standard DFT and ATPG tools.
• Strong problem‑solving skills and the ability to collaborate across design teams.

(ref:hirist.tech)