DFT Engineer

Weekday AI (YC W21); Bengaluru; On-site; INR 1,500,000 - 8,000,000; Full time

Job summary

Weekday AI is seeking an experienced DFT Engineer for a client project in Bengaluru. The role focuses on defining and implementing DFT strategies for complex ASIC/SoC designs, with hands-on ATPG, Scan insertion, and verification across RTL to physical design.

The ideal candidate has 5+ years of industry experience, strong scripting skills, and a deep understanding of test coverage and fault models. Opportunity to influence silicon readiness and post-silicon debug may be involved.

Qualifications

• 5-20 years of hands-on DFT/ASIC design and test engineering.
• Strong expertise in ATPG and Scan architectures.
• Experience debugging ATPG patterns and DFT rule violations.
• Collaboration with RTL, synthesis, verification and physical design teams.

Responsibilities

• Define and implement DFT architectures for complex ASIC/SoC designs.
• Develop and integrate Scan-based DFT structures across blocks and top-level designs.
• Develop, run, and debug ATPG flows for stuck-at, transition, and other fault models.
• Analyze ATPG coverage, fault reports, pattern quality, and test compression results.
• Collaborate with physical design teams to ensure timing-aware DFT structures.
• Support scan insertion, scan-chain verification, and chain balancing.
• Develop and maintain DFT methodologies, scripts, and automation.

Skills

ATPG

Scan architecture

Scan insertion

DFT/ASIC design

RTL/SoC flows

Scripting (Python)

Scripting (Perl)

Scripting (Tcl)

Test coverage

Tools

ATPG tools

Job description

This role is for one of the Weekday's clients

Salary range: Rs 1500000 - Rs 8000000 (ie INR 15 - 80 LPA)

Min Experience: 5+ years

Location: Bengaluru, Telangana, Hyderabad, Telangana, India, Karnataka

JobType: full-time

We are seeking an experienced DFT Engineer with 5-20 years of industry experience to drive the design-for-test strategy and implementation for complex ASIC/SoC designs. The ideal candidate will have strong hands-on expertise in ATPG and Scan, with a solid understanding of test architecture, fault coverage, test pattern generation, and DFT verification.

Requirements

Key Responsibilities

• Define and implement DFT architectures for complex ASIC/SoC designs
• Develop and integrate Scan-based DFT structures across blocks and top-level designs
• Develop, run, and debug ATPG flows for stuck-at, transition, and other relevant fault models
• Analyze ATPG coverage, fault reports, pattern quality, and test compression results
• Debug ATPG failures and identify design, constraint, or test-logic issues
• Work with RTL and design teams to resolve DFT-related implementation and verification issues
• Perform DFT rule checks and ensure test structures meet project requirements
• Support scan insertion, scan-chain verification, chain balancing, and scan connectivity checks
• Collaborate with physical design teams to ensure DFT structures are physically implementable and timing-aware
• Support DFT verification from block level through full-chip integration
• Develop and maintain DFT methodologies, scripts, and automation to improve design and test efficiency
• Participate in test architecture reviews and contribute to improving test coverage, quality, and overall silicon readiness
• Support post-silicon debug and analysis of test-related issues when required

Must-Have Skills

• 5-20 years of hands-on experience in DFT/ASIC design and test engineering
• Strong expertise in ATPG (Automatic Test Pattern Generation)
• Extensive experience with Scan architecture and Scan insertion
• Strong understanding of scan chains, scan compression, test modes, and test coverage
• Experience debugging ATPG patterns, coverage issues, and DFT rule violations
• Good understanding of ASIC/SoC design flows and DFT implementation methodologies
• Experience working with RTL, synthesis, verification, and physical design teams
• Strong scripting/automation skills using languages such as Tcl, Python, or Perl

Good-to-Have Skills

• Experience with SSN (Serial Scan Network) and related test architectures
• Knowledge of PDL (Procedure Description Language) and IEEE 1687/IJTAG concepts
• Experience with DRC (Design Rule Checks) for DFT/test structures
• Exposure to memory BIST, logic BIST, boundary scan, test compression, and IEEE 1149.x standards
• Experience with industry-standard DFT/ATPG tools and methodologies
• Understanding of timing, power, and physical-design considerations for scan and ATPG
• Experience with advanced SoC designs and hierarchical DFT implementation

What We're Looking For

The ideal candidate is a technically strong DFT professional who can independently own DFT activities, troubleshoot complex test challenges, and collaborate effectively across multiple engineering teams. Strong analytical, debugging, communication, and problem-solving skills are essential for success in this role.