Senior Design Verification Engineer

Ciliconchip; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Ciliconchip in Bengaluru, India seeks a verification engineer to lead IP/subsystem verification. You will build UVM environments, develop monitors, scoreboards and drivers, and drive systematic regression and coverage closure.

You will mentor junior engineers while collaborating with cross-functional teams on PCIe, USB, DDR, and Ethernet IP blocks, applying SystemVerilog, UVM/OVM, and advanced assertion and coverage techniques to ensure high quality silicon.

Qualifications

• Strong hands-on UVM/OVM and SystemVerilog verification.
• SVA and functional coverage modeling experience.
• Familiarity with PCIe/USB/DDR/Ethernet IP protocols.
• Scripting in Python/Perl/TCL.

Responsibilities

• Lead IP/subsystem verification, build UVM environments (monitors, scoreboards, drivers), track coverage closure, run regressions, and mentor junior engineers.

Skills

UVM / OVM

SystemVerilog

Constrained-Random Verification

SVA & Functional Coverage modeling

PCIe / USB / DDR / Ethernet protocols

Python / Perl / TCL scripting

Tools

Xcelium

VCS

Questa

Verdi

SimVision

Job description

• Methodologies: Strong hands-on UVM / OVM and SystemVerilog (Constrained-Random Verification)
• Assertions & Coverage: SystemVerilog Assertions (SVA) & Functional Coverage modeling
• Protocols (Any): PCIe, USB, DDR, or Ethernet
• EDA Tools: Xcelium, VCS, or Questa
• Debug Tools: Verdi or SimVision
• Scripting: Python, Perl, or TCL

What You'll Do:

• Lead IP/subsystem verification, build UVM environments (monitors, scoreboards, drivers), track coverage closure, run regressions, and mentor junior engineers.