Senior Design Verification Engineer - SOC/IP/Formal

L&T Technology Services; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

A leading technology services firm in Bengaluru is looking for a skilled Verification Engineer. The ideal candidate should have 6-7 years of experience in functional verification, particularly with SystemVerilog/UVM, and a strong grasp of verification techniques. Responsibilities include developing verification infrastructures and writing testbenches. If you're passionate about innovation and have excellent communication skills, apply now to join a dynamic team focused on solving challenging problems.

Qualifications

• 6-7 years of experience in functional verification of blocks/systems using SystemVerilog/UVM.
• Strong understanding of verification techniques including assertions.
• Experience in developing full verification infrastructure from scratch.

Responsibilities

• Work closely with design architecture team on performance verification.
• Develop verification infrastructure involving VIPs and memory models.
• Write configurable testbenches in SystemVerilog/UVM.

Skills

SystemVerilog/UVM

Debugging RTL and testbenches

Coverage-driven verification methodology

Verification techniques

Script languages (perl/python)

Tools

Jenkins

Gitlab CI

Circle CI

Emulators

AXI4

Job description

Responsibilities

• Working closely with the design architecture team and contributing to IP, performance and SoC related verification.
• Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.
• Writing configurable testbenches in SystemVerilog/UVM and testbench automation.
• Writing SystemVerilog assertions and maintaining them.
• Writing functional coverage and overall functional and code coverage analysis.
• Working on ASIC power estimation and power-aware verification.
• Working on Gate Level Simulation and Emulators
• Automating tool flows and creation of result reports.

Desired Qualifications:

• 6-7 years of experience in functional verification of blocks/systems using SystemVerilog/UVM.
• Strong understanding of verification techniques including assertions, metric-driven and coverage-driven verification.
• Experience in developing full verification infrastructure from scratch.
• Experience with verification of systems which involve high-speed buses such as AXI4.
• Verification Experience on PCIe or DDR
• Working knowledge of Emulator based verification.
• Experience with gate level simulations and delay modeling.
• Experience with constraint random verification.
• Experience with writing functional coverage and overall code coverage analysis.
• Experience with coverage-driven verification methodology.
• Experience in writing and debugging SystemVerilog assertions.
• Strong experience in debugging RTL and testbenches.

Preferred Qualifications:

• Prior experience in working with VIPs and verification environments which involve VIPs.
• Prior experience in verifying IPs/systems which include PCI-E/DDR (any) protocol.
• Experience with SoC level verification.
• Experience in using Continuous Integration tools such as Jenkins, Gitlab CI, Circle CI.
• Emulation based verification
• Experience with scripting languages such as perl/python.

Looking for someone who is passionate to innovate and execute, a high-gear individual with multi-tasking capabilities, ready to solve challenging problems. Ideal candidate is a person who is personable, self-motivated and has excellent written and verbal communication skills.