Lead Design Verification Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru is seeking an experienced verification engineer to own IP/SoC verification from planning to coverage closure and signoff.

You will develop scalable SystemVerilog/UVM testbenches and VIPs, drive architecture, constrained-random verification, and regression, ensuring first-pass silicon success through collaboration with RTL, firmware, and post-silicon teams.

Qualifications

• 7-12 years of IP/SoC verification experience.
• Expert in SystemVerilog, UVM, TB Architecture, SVA, Functional Coverage.
• Experience verifying high-speed protocols such as PCIe, CXL, DDR, LPDDR, USB, Ethernet, UCIe, or MIPI.
• Proficiency with VCS, Xcelium or Questa, and waveform/debug tools like Verdi/DVE.
• Strong debugging and scripting with Python, Perl, or Tcl.

Responsibilities

• Own verification of IP/SoC from planning to coverage closure and signoff.
• Develop scalable SystemVerilog/UVM testbenches, VIPs, scoreboards, and assertions (SVA).
• Drive testbench architecture, constrained-random verification, regression, debug, and verification closure.
• Verify high-speed protocols including PCIe, CXL, DDR4/5, LPDDR4/5, USB3/USB4, Ethernet, UCIe, MIPI, AXI/AHB/APB.
• Collaborate with RTL, Architecture, Firmware, DFT, Emulation, and Post-Silicon teams to achieve first-pass silicon success.
• Mentor engineers and drive verification best practices across programs.

Skills

SystemVerilog

UVM

Testbench Architecture

SVA

Functional Coverage

Constrained Random Verification

PCIe

CXL

DDR4/DDR5

LPDDR4/LPDDR5

USB3/USB4

Ethernet

UCIe

MIPI

AXI/AHB/APB

Verdi/DVE

Python

Perl

Tcl

VCS

Xcelium

Questa

Tools

VCS

Xcelium

Questa

Verdi/DVE

Job description

Lead the verification of complex IPs and SoCs, driving end-to-end verification strategy, methodology, and signoff for high-performance silicon.

What You'll Do

• Own verification of IP/SoC from planning to coverage closure and signoff.
• Develop scalable SystemVerilog/UVM testbenches, VIPs, scoreboards, assertions (SVA), and functional coverage.
• Drive testbench architecture, constrained-random verification, regression, debug, and verification closure.
• Verify high-speed protocols including PCIe, CXL, DDR4/DDR5, LPDDR4/5, USB3/USB4, Ethernet, UCIe, MIPI, AXI/AHB/APB.
• Collaborate with RTL, Architecture, Firmware, DFT, Emulation, and Post-Silicon teams to achieve first-pass silicon success.
• Mentor engineers and drive verification best practices across programs.

What You Bring

• 7-12 years of hands-on IP/SoC Design Verification experience.
• Expert in SystemVerilog, UVM, Testbench (TB) Architecture & Coding, SVA, Functional Coverage, and Constrained Random Verification.
• Strong experience verifying one or more high-speed protocols such as PCIe, CXL, DDR, LPDDR, USB, Ethernet, UCIe, or MIPI.
• Proficiency with VCS, Xcelium or Questa, and waveform/debug tools such as Verdi/DVE.
• Strong debugging, scripting, and problem-solving skills with exposure to Python, Perl, or Tcl.

Preferred

• Experience with SoC integration, Low-Power (UPF), CDC/RDC, Formal Verification, or Emulation.
• Experience mentoring engineers and driving technical reviews.

We're looking for engineers who build robust verification infrastructure, solve complex silicon challenges, and deliver first-pass silicon success through technical excellence.