Senior Design Verification Engineer

eInfochips (An Arrow Company); Hyderabad; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

eInfochips (An Arrow Company) seeks an experienced SoC verification engineer to develop and run SystemVerilog/UVM testbenches for multi-core digital SoCs. Automotive IP such as Ethernet/CAN/LIN is a plus. Independent work with minimal supervision and collaboration with the team are required.

Responsibilities include creating testcases, verification plans, coverage metrics, assertions, and automatic reporting, plus regression setup and JIRA issue tracking.

Qualifications

• Experience in digital multi-core SoC verification
• Proficiency with SystemVerilog/UVM is a plus
• Strong scripting skills (Shell/Perl/Python)

Responsibilities

• Code testcases for SoC verification using SystemVerilog (UVM) and C
• Develop and maintain UVM environments, assertions, covergroups and checkers
• Generate verification plans from specifications and track coverage
• Set up regressions, analyze failures and file JIRA tickets

Job description

• Coding of testcase for SoC using SystemVerilog (UVM) & C
• SoC Level verification is a must.
• AMBA bus protocol like AHB, AXI is a must.
• Generate Verification Plan from the Specifications using vManager.
• Determine Coverage and design completeness requirements.
• Generate random-constraint tests to meet coverage requirements.
• Create Assertions, cover-groups, checkers, monitors and automatic reporting.
• Set-up and run regression, analyze/debug the failure and file JIRA.

Job Requirements

• BSEE (MSEE pref.) or equivalent with 5 to 9 years professional industry experience in Digital multi core SoC verification.
• AUTOMOTIVE SOC is plus – IP like Ethernet, CAN, LIN and MRAM and so on.
• UVM testbench creation, writing and implementation is a plus.
• Proficient developing scripts (Shell, Perl, Python etc.), and Cadence SKILL language is plus
• Must be able to work independently with limited supervision and work closely with team.