Design Verification Engineer

Erbity Private Limited; India; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Erbity Private Limited is seeking a meticulous and highly analytical Design Verification Engineer to join our distributed engineering team. You will be responsible for ensuring the structural integrity, functionality, and performance of our hardware/system designs through rigorous testing and automated validation frameworks.

Key responsibilities include test strategy and execution, defect management, data analysis, automation and tooling, cross-functional collaboration, documentation, and

Qualifications

• Proven experience in hardware verification and testbench development.
• Strong knowledge of SystemVerilog/UVM and HDL languages.
• Experience with CI/CD pipelines and automated testing.

Responsibilities

• Develop, execute, and refine test plans to verify designs meet specifications.
• Identify, document, and track design defects; drive issues to resolution.
• Analyze test results and data to inform design optimization.
• Design and implement automated test scripts and scalable verification frameworks.
• Collaborate with engineering teams to validate requirements and downstream implementation.
• Create and maintain verification documentation including plans and traceability.
• Contribute to design-for-testability improvements during reviews.

Skills

Analytical mindset

Attention to detail

Tools

SystemVerilog

UVM

Verilog

VHDL

Python

Perl

Tcl

Synopsys VCS

Cadence Xcelium

Siemens Questa

Verdi

SVA

PCIe

AMBA AXI/AHB

USB

DDR

Job description

We are seeking a meticulous and highly analytical Design Verification Engineer to join our distributed engineering team. In this role, you will be responsible for ensuring the structural integrity, functionality, and performance of our hardware/system designs through rigorous testing and automated validation frameworks.

Key Responsibilities

• Test Strategy & Execution: Develop, execute, and refine comprehensive test plans and procedures to verify that designs meet all functional and performance specifications.
• Defect Management: Proactively identify, document, and track design defects. Collaborate closely with designers and stakeholders to drive issues to resolution.
• Data Analysis: Analyze complex test results and datasets to uncover patterns or trends, providing actionable recommendations for design optimization.
• Automation & Tooling: Design and implement automated test scripts and scalable test frameworks to maximize verification efficiency and coverage.
• Cross-functional Collaboration: Partner with engineering teams to ensure all requirements are fully validated and that designs are implemented correctly in downstream departments.
• Documentation & Compliance: Create and maintain high-quality technical documentation, including traceability matrices, test reports, and verification plans.
• Design Influence: Participate in design reviews, offering expert feedback on requirements and ensuring "design-for-testability" (DFT) principles are met.

Requirements

• Hardware Description & Verification Languages: Extensive experience with SystemVerilog and UVM (Universal Verification Methodology) is required. Proficiency in Verilog or VHDL for design understanding.
• Scripting & Automation: Strong command of Python, Perl, or Tcl for developing automated test scripts and maintaining CI/CD pipelines.
• Simulation & Debugging: Proficiency with industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Siemens Questa). Expertise in debugging using Verdi or similar waveform viewers.
• Verification Techniques: Experience with constrained-random verification, assertion-based verification (SVA), and functional coverage (code and covergroups).
• Protocol Knowledge: Familiarity with high-speed interface protocols such as PCIe, AMBA (AXI/AHB), USB, or DDR.