Senior Engineer Design Verification

Brain Links & Resources; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Brain Links & Resources in Bengaluru, India, seeks a Senior Engineer Design Verification to lead verification strategies for complex ASIC/FPGA designs. You will build UVM-based environments and develop coverage-driven tests to ensure robust silicon.

The ideal candidate has 6–8 years in design verification, strong SystemVerilog, UVM, SVA, and UVC development experience, plus a track record with international projects.

Qualifications

• 6-8 years of overall experience in Design Verification.
• 6+ years of hands-on experience in Logic Design Verification.
• 3+ years of hands-on experience in SystemVerilog UVM.
• Strong hands-on experience with SystemVerilog.
• Strong knowledge of UVM methodology and UVC development/integration.
• Strong experience in SystemVerilog Assertions (SVA).
• Strong experience in Functional Coverage and Coverage Closure.
• Experience in ASIC and/or FPGA verification.
• Good scripting skills in Python, Perl, TCL or BASH.
• Good working experience with Linux.
• Experience with version-control tools such as Git, SVN, CVS, Perforce or ClearCase.
• Minimum 2 years of experience working on international projects.
• Strong debugging and problem-solving skills.

Responsibilities

• Develop requirement-oriented verification and test plans.
• Develop and maintain SystemVerilog UVM verification environments.
• Develop and integrate UVCs.
• Develop coverage-driven tests and drive functional coverage closure.
• Develop and implement SystemVerilog Assertions (SVA).
• Perform stress and performance testing.
• Debug design and verification issues and identify root causes.
• Work closely with Logic Design Engineers on specifications and verification requirements.
• Track verification progress and report project status, risks and challenges.
• Support CI and verification infrastructure as required.

Skills

SystemVerilog

UVM

SVA

Functional Coverage

UVC development

ASIC verification

FPGA verification

Python

Linux

Git

Education

Bachelor's degree in Computer Science, Electrical Engineering, Electronics Engineering, Software Engineering or related discipline

Tools

Git

SVN

CVS

Perforce

ClearCase

Job description

ob Description:

We are looking for an experienced Senior Engineer Design Verification with strong hands-on expertise in Logic Design Verification, SystemVerilog, UVM, Functional Coverage and SystemVerilog Assertions (SVA).

The candidate will be responsible for developing and executing verification strategies, building UVM-based verification environments, developing coverage-driven tests, debugging design issues and working closely with Logic Design Engineers.

Key Responsibilities:

• Develop requirement-oriented verification and test plans
• Develop and maintain SystemVerilog UVM verification environments
• Develop and integrate UVCs
• Develop coverage-driven tests and drive functional coverage closure
• Develop and implement SystemVerilog Assertions (SVA)
• Perform stress and performance testing
• Debug design and verification issues and identify root causes
• Work closely with Logic Design Engineers on specifications and verification requirements
• Track verification progress and report project status, risks and challenges
• Support CI and verification infrastructure as required

Required Skills & Experience:

• 6-8 years of overall experience in Design Verification
• 6+ years of hands-on experience in Logic Design Verification
• 3+ years of hands-on experience in SystemVerilog UVM
• Strong hands-on experience with SystemVerilog
• Strong knowledge of UVM methodology and UVC development/integration
• Strong experience in SystemVerilog Assertions (SVA)
• Strong experience in Functional Coverage and Coverage Closure
• Experience in ASIC and/or FPGA verification
• Good scripting skills in Python, Perl, TCL or BASH
• Good working experience with Linux
• Experience with version-control tools such as Git, SVN, CVS, Perforce or ClearCase
• Minimum 2 years of experience working on international projects
• Strong debugging and problem-solving skills

Qualification:

Bachelor's degree in Computer Science, Electrical Engineering, Electronics Engineering, Software Engineering or a related discipline.