Analog layout Engineer- Bangalore

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru, India is seeking an experienced analog/mixed-signal layout engineer to design layouts for advanced nodes (28nm and below). You will perform custom layout, floorplanning, placement and routing, and work with circuit design and verification teams to meet tape-out deadlines.

Responsibilities include ensuring DRC/LVS/ERC/PEX, matching, symmetry, shielding, and layout techniques; optimizing for area and performance; and sign-off.

Qualifications

• Strong experience in Analog/Mixed-Signal Layout.
• Hands-on with lower-node technologies.
• Understanding of MOS, resistor, capacitor, current mirror and differential pair layouts.
• Experience with Cadence Virtuoso / Custom Compiler or equivalent tools.
• Proficient in DRC, LVS, ERC and PEX.
• Knowledge of advanced matching and layout techniques.

Responsibilities

• Design and develop analog/mixed-signal layouts for advanced technology nodes.
• Perform custom layout, floorplanning, placement and routing of analog blocks.
• Ensure layout quality with matching, symmetry, shielding and guard rings.
• Handle DRC, LVS, ERC and PEX and resolve layout issues.
• Collaborate with Circuit Design, Physical Design, Verification and Tech teams.
• Optimize layouts for area, performance, parasitics and reliability.
• Support tape-out activities and layout sign-off.

Skills

Analog/Mixed-Signal Layout

Lower-node technologies

MOS/Resistor/Capacitor layouts

DG/CG matching techniques

Cadence Virtuoso / Custom Compiler

DRC/LVS/ERC/PEX

Advanced-node layout knowledge

Tools

Cadence Virtuoso

Custom Compiler

Job description

• Design and develop analog/mixed-signal layouts for advanced technology nodes.


• Work on lower-node technologies such as 28nm, 16nm, 7nm, 5nm and below.


• Perform custom layout, floorplanning, placement and routing of analog/mixed-signal blocks.


• Handle matching, common-centroid, symmetry, shielding, guard rings and sensitive analog layout techniques.


• Perform DRC, LVS, ERC and PEX and resolve layout-related issues.


• Collaborate closely with Circuit Design, Physical Design, Verification and Technology teams.


• Optimize layouts for area, performance, parasitics and reliability.


• Support tape-out activities and ensure quality/layout sign-off.

Required Skills

• Strong experience in Analog/Mixed-Signal Layout.


• Hands-on experience with lower-node technologies.


• Good understanding of MOS, resistor, capacitor, current mirror, differential pair and analog IP layouts.


• Experience with Cadence Virtuoso / Custom Compiler or equivalent tools.


• Strong knowledge of DRC, LVS, ERC and PEX.


• Understanding of advanced matching and layout techniques.


• Exposure to FinFET / advanced-node layout is an added advantage.

Preferred

• Experience in SerDes, PLL, ADC/DAC, PMIC, Memory or high-speed analog blocks.


• Experience working on 7nm/5nm/3nm or other advanced process nodes.


• Good communication and cross-functional collaboration skills.