Analog Layout Engineer II

leadIC Design Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

A semiconductor design company in Bengaluru is looking for an Analog Layout Design Engineer with 6–8 years of experience in analog layout design, specifically for TSMC process nodes. The candidate must possess strong skills in layout techniques for high-speed, low-power circuits, and proficiency in tools like Cadence Virtuoso and Calibre. This full-time role involves collaboration with circuit designers and ensuring compliance with foundry requirements.

Qualifications

• 6–8 years of hands-on experience in Analog Layout Design.
• Experience in TSMC nodes (3nm / 5nm / 7nm / 12nm / 16nm).
• Strong expertise in layout techniques for high-speed, low-power, and high-precision analog circuits.

Responsibilities

• Perform full-custom analog layout design for various blocks.
• Work on deep sub-micron process nodes ensuring compliance with foundry rules.
• Execute layout of matched devices and perform LVS/DRC verification.

Skills

Analog Layout Design

TSMC nodes

Layout techniques

Debugging and problem-solving

Communication and teamwork

Tools

Cadence Virtuoso

Calibre

Assura

Mentor tools

Job description

Role: Analog Layout Design Engineer
Experience: 6–8 years
Industry: Semiconductor / VLSI
Location: Bengaluru
Job Type: Full-time

Responsibilities

• Perform full-custom analog layout design for blocks such as PLLs, ADCs, DACs, SerDes, High-Speed IOs, Power Management Circuits, and Standard Cells.

• Work on deep sub-micron process nodes (TSMC 3nm to 16nm) ensuring compliance with foundry rules.

• Execute layout of matched devices, current mirrors, differential pairs, and high-precision analog/mixed-signal circuits.

• Perform floorplanning, placement, routing, parasitic extraction, and LVS/DRC verification.

• Collaborate with circuit designers to ensure performance, reliability, and yield requirements are met.

• Work on layout optimization for area, performance, and manufacturability (DFM).

• Support design reviews and contribute to timely tape-outs.

• Interface with foundries and EDA vendors when required.

Requirements

• 6–8 years of hands-on experience in Analog Layout Design.

• Experience in TSMC nodes (3nm / 5nm / 7nm / 12nm / 16nm).

• Strong expertise in layout techniques for high-speed, low-power, and high-precision analog circuits.

• Proficiency in Cadence Virtuoso, Calibre (LVS/DRC), Assura, Mentor tools.

• Good understanding of matching, shielding, symmetry, guard rings, and latch-up prevention techniques.

• Knowledge of parasitic effects, EM/IR drop, and reliability constraints.

• Strong debugging and problem-solving skills.

• Excellent communication and teamwork skills.

Good to Have

• Experience with RF and Mixed-Signal layout.

• Prior experience working in analog IP development or product companies.

• Exposure to FinFET layout challenges (TSMC 7nm and below).

• Familiarity with global tape-out cycles.