RTL Design Engineer

Vikarna Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Vikarna Technologies in Bengaluru is seeking a semiconductor design engineer to own micro-architecture and synthesizable RTL for IP and subsystem blocks, ensuring lint, CDC, and synthesis readiness.

You will translate specifications into micro-architecture, write and review synthesizable SystemVerilog RTL, and help close lint, CDC, and synthesis constraints while supporting integration and debugging with DV teams.

Qualifications

• Exposure to synthesis and timing concepts.

Responsibilities

• Translate specifications into micro-architecture
• Write and review synthesizable SystemVerilog RTL
• Close lint, CDC, and synthesis constraints
• Support integration and debug with DV teams

Skills

SystemVerilog

RTL design

Lint / CDC

Synthesis

Job description

Own micro-architecture and synthesizable RTL for IP and subsystem blocks, through lint, CDC, and synthesis readiness.

Semiconductor Design Bangalore / Hyderabad Full-time 2-6 years

What this role covers

Own micro-architecture and synthesizable RTL for IP and subsystem blocks, through lint, CDC, and synthesis readiness.

Responsibilities

• Translate specifications into micro-architecture
• Write and review synthesizable SystemVerilog RTL
• Close lint, CDC, and synthesis constraints
• Support integration and debug with DV teams

Requirements

Exposure to synthesis and timing concepts