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Cyient in Bengaluru is seeking an experienced RTL design engineer to develop RTL in Verilog/SystemVerilog, translating architecture specs into realizable designs and collaborating with cross-functional teams.
You will work on motor control, industrial interfaces, embedded controllers, and a range of interfaces (UART, SPI, I2C, CAN, Ethernet) while supporting verification, DFT, synthesis, and physical design handoffs.