RTL Architect: SOC Architect

Mirafra Technologies; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Mirafra Technologies in Bengaluru seeks a seasoned SoC Architect to define system and micro-architectures, own top-level integration, and coordinate across CPU/memory subsystems and interconnects.

You will drive low-power techniques, DFT/debug, and formal verification, while mentoring engineers and ensuring delivery of complex SoC programs in a fast-paced environment.

Qualifications

• Expertise in translating product requirements into scalable micro-architectures.
• Proven experience in top-level SoC integration and cross-IP coordination.
• Strong knowledge of AXI/ACE/PCIe interconnects and DFT/debug infrastructures.
• Hands-on RTL design and SystemVerilog coding practices for reusable, synthesis-friendly code.
• Experience in timing closure, STA, and ECO handling across PVT corners.
• Ability to mentor engineers and drive delivery of complex SoC programs.

Responsibilities

• Translate product requirements into scalable, power- and performance-optimized micro-architectures.
• Own SoC integration, clock/reset planning, and cross-IP coordination.
• Lead verification strategies, tests, and regression quality metrics.
• Drive synthesis, STA, and timing closure across multiple PVT corners.
• Collaborate with firmware and software teams for hardware/software co-design.
• Mentor engineers and drive best practices across SoC programs.

Skills

System & Micro-Architecture

SoC Integration

Bus Protocols

CPU & Memory Subsystems

Low-Power Architecture

RTL Design

Verification & Sign-off

Synthesis & STA

Formal Verification

DFT & Debug

Post-Silicon Bring-up

Chip IO & Packaging

Cross-Functional Leadership

Mentoring

Embedded HW/SW Co-design

Education

BTech/ MTech Electrical/Electronics/Computer Science Engineering or Equivalent

Tools

Design Compiler

Job description

• System & Micro-Architecture Definition: Proven ability to translate product requirements and specifications into scalable, power- and performance-optimized micro-architectures.
• SoC Integration & Sub-System Ownership: Extensive experience in top-level SoC integration, clock/reset architecture, power domain planning, and cross-IP coordination.
• Bus Protocols & Interconnects: Strong expertise in industry-standard protocols such as AXI/AHB/APB, coherent interconnects (ACE/CHI preferred), and peripherals including PCIe, USB, Ethernet, CXL, and DDR.
• CPU & Memory Subsystems: Hands-on experience with CPU subsystem integration (ARM/ARC/RISC-V), cache hierarchy, MMU, and memory controller architectures (DDR, LPDDR).
• Low-Power Architecture: Deep understanding of low-power techniques including UPF/CPF, power gating, clock gating, DVFS, multi-voltage designs, and retention strategies.
• RTL Design & Coding Practices: Strong System Verilog RTL coding skills with emphasis on reuse, configurability, and synthesis-friendly design.
• Verification & Quality Sign-off: Ability to review and guide verification strategy, static checks test plans, functional coverage, assertions, and regression quality metrics.
• Synthesis, STA & Sign-off: Expertise in synthesis (Design Compiler), static timing analysis, timing closure across multiple PVT corners, and ECO handling.
• Formal & Equivalence Checking: Strong experience with formal verification and logical equivalence checking (LEC).
• DFT & Debug: Good working knowledge of DFT architectures (scan, MBIST, JTAG) and debug/trace infrastructures.
• Post-Silicon Bring-up: Experience with silicon bring-up, lab debugging, silicon validation, and correlation between RTL, simulation, and silicon behaviour.
• Chip IO & Packaging: Understanding of chip IO planning, pad ring integration, signal integrity considerations, and packaging constraints.
• Cross-Functional Leadership: Ability to work closely with PD, DV, DFT, firmware, and software teams to ensure seamless execution and delivery.
• Mentoring & Technical Leadership: Proven capability to mentor engineers, review designs, drive best practices, and own delivery of complex SoC programs.
• Embedded hardware and software co-design: Collaborate with embedded software and firmware teams to ensure hardware and software co-design, enabling efficient SoC architecture.

Education

• BTech/ MTech Electrical/Electronics/Computer Science Engineering or Equivalent.