SOC Digital Design Architect - RTL

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,200,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd is seeking a senior SoC Architect to lead micro-architecture, block design, and IP integration for production-grade silicon. You will drive RTL/UPF development, timing constraints, and DFT/PD planning, collaborating with the FW team to ensure successful silicon delivery.

The role requires a deep understanding of Verilog/VHDL, high-speed SerDes, bus protocols, and power management, with a strong track record of shipping complex SoCs to production.

Qualifications

• CS/EE/EC engineering graduate or postgraduate with 15+ years of relevant experience.
• Proven track record of micro-architecting and designing a complex SoC to production.
• Hands-on RTL design, linting, UPF coding, and delivering synthesizable RTL.

Responsibilities

• Responsible for micro-architecture, MRD understanding, and top-level architecture and block diagrams.
• Develop and deliver RTL, UPF, timing constraints, and DFT/PD implementations.
• Work with SoC leads to integrate designs and set up FPGA flows; review DV and PD plans.

Skills

Verilog

VHDL

High Speed SerDes

Bus protocols

Clock & power management

RTL design

Verification guidance

Education

CS/EE/EC Engg + 15+ yrs exp

Tools

Version control systems

Job description

• Responsibility for Micro architecture , Spec / MRD understanding
• Top level Architecture and Block Diagram
• SoC Fabrics, Protocol Bridges
• Fuse, Boot, Security
• IP planning and interfaces
• Pinout, ball mapping
• Systems and Test planning
• Design feasibility and PPA analysis
• Develop details for micro architecture for the target SoC to meet chip specifications.
• Write MAS / PRD document, drive alignment for IPs with reviews to signoff.
• Develop and work with the team to deliver RTL, UPF, timing constraints.
• Work with SoC lead to integrate the design and setup the FPGA flows
• Review DV, DFT and PD implementation plans for sign-off.

Skills:

• Verilog, VHDL, High Speed SerDes protocols understanding, Bus protocols, Clock & power management etc.
• Proven track record of having Micro architected, Designed a complex SoC to production
• RTL design process: Specifying microarchitecture, developing RTL, linting, UPF coding, delivering synthesizable RTL, guiding Verification, DFT and PD implementations of the design.
• Awareness in comprehensive validation techniques of the specific design domain.
• Ability to review and signoff implementation of the design.
• Hands-on experience working with version control systems.
• Work with the FW development team for the design – as required.
• Scripting experience for efficiency and quality.

Education & Experience:

• CS/ EE/ EC Engineering Graduate or postgraduate with 15+ years of relevant experience.