Chip Top Level RTL Lead

HCLTech; Hyderabad, Chennai District, Bengaluru; Hybrid; INR 4,000,000 - 7,000,000; Full time

Job summary

HCLTech is seeking a Chip Top-Level RTL Integration Lead to own the integration of multi-IP SoCs, aligning architecture, design, verification, and physical teams toward successful tapeout. The role focuses on clean connectivity, robust interfaces, and CDC/lint readiness, with collaboration across DV and PD teams to ensure a seamless system bring-up.

The ideal candidate has deep RTL experience, proficiency in Verilog/SystemVerilog, and a strong grasp of NoC/bus interconnects, clock/reset, and

Qualifications

• Strong expertise in Verilog/SystemVerilog RTL design and SoC integration.
• Deep understanding of AXI/AHB/APB bus protocols and interconnects.
• Experience with clock/reset domain design and low-power UPF/CPF basics.

Responsibilities

• Own top-level RTL integration of SoC and ensure clean connectivity and hierarchy.
• Coordinate with architecture, DV, DFT and PD teams for tapeout readiness.
• Define and validate interfaces and protocols (AXI, AHB, APB) across IPs and subsystems.
• Drive lint, CDC/RDC analysis, and basic synthesis checks for RTL quality.
• Lead debugging of integration issues and support system bring-up in simulation/emulation.

Skills

Verilog/SystemVerilog

SoC integration

AXI/AHB/APB

Clock/reset domain design

Low-power design UPF/CPF

Lint/CDC/RDC tools

Synthesis awareness

RTL debugging

Education

Bachelor's degree in Electrical Engineering / Computer Engineering

Tools

SpyGlass

Questa Lint

SpyGlass CDC

Questa CDC

Design Compiler

Genus

Git/Perforce

Job description

Chip Top-Level RTL Integration Lead -FYR

Role Overview

Lead and own SoC RTL integration for complex chips, ensuring seamless assembly of multiple IPs/subsystems into a functionally correct, synthesis-ready top-level design. This role is central to aligning architecture, design, verification, and physical teams for successful tapeout.

Key Responsibilities

RTL Integration Ownership

• Own top-level RTL integration of SoC:
• Integrate multiple IPs, subsystems, and third-party blocks
• Ensure clean connectivity, hierarchy, and modular structure
• Deliver synthesis-ready, lint-clean, and CDC-clean RTL

Architecture Alignment

• Work closely with architecture teams to:
• Translate SoC architecture into RTL structure
• Ensure correct implementation of:
• Interconnects (NoC / bus-based)
• Address maps
• Reset and clock architecture

Interface & Connectivity Management

• Define and validate:
• IP interfaces and protocols (AXI, AHB, APB, etc.)
• Address decoding and interconnect connectivity
• Resolve:
• Interface mismatches
• Integration conflicts across teams

Clock, Reset & Power Integration

• Define and integrate:
• Clocking architecture (multiple clock domains)
• Reset strategies (global/local resets)
• Power domains (UPF/CPF alignment)
• Ensure:
• Clean CDC/RDC implementation
• Proper low-power intent integration

Quality & Signoff Readiness

• Drive RTL quality checks:
• Lint (SpyGlass, Lint tools)
• CDC/RDC analysis
• Basic synthesis checks
• Ensure RTL is:
• DV-ready
• DFT-ready
• PD-friendly

Collaboration Across Teams

• Interface with:
• IP/RTL design teams
• DV teams (for testbench integration support)
• DFT teams (for scan/test readiness)
• PD/STA teams (for implementation alignment)
• Act as central integration point across all domains

Debug & Issue Resolution

• Lead debug of:
• Integration bugs
• Boot-up and reset sequence issues
• Connectivity and functional mismatches
• Support system-level bring-up in simulation/emulation

Automation & Flow Development

• Develop scripts/tools for:
• RTL stitching
• Connectivity checks
• Build and regression flows
• Improve integration efficiency and repeatability

Leadership

• Lead and mentor RTL integration engineers
• Drive integration schedules, milestones, and reviews
• Act as owner of top-level RTL quality and readiness

Required Skills & Expertise

Technical

• Strong expertise in:
• Verilog/SystemVerilog RTL design
• SoC integration and architecture
• Deep understanding of:
• Bus protocols (AXI/AHB/APB)
• Clock/reset domain design
• Low-power design (UPF/CPF basics)
• Experience with:
• Lint, CDC/RDC tools
• Synthesis awareness

Experience

• 1218+ years in RTL design/integration
• Proven experience in:
• Chip-level RTL integration ownership
• Multiple SoC tapeouts

Tools

• Lint: SpyGlass / Questa Lint
• CDC: SpyGlass CDC / Questa CDC
• Synthesis: Design Compiler / Genus (basic awareness)
• Version control: Git/Perforce

Soft Skills

• Strong system-level thinking
• Excellent coordination across large teams
• Problem-solving and debugging mindset

Good to Have

• Experience in:
• NoC-based SoC architectures
• Emulation/FPGA bring-up
• Firmware/boot flow understanding

Scripting:

• Python / TCL / Perl

Success Metrics

• Clean, integration-ready RTL (lint/CDC clean)
• Smooth handoff to DV, DFT, and PD teams
• Minimal integration bugs at system level
• Predictable integration schedules
• First-pass success in SoC bring-up