Senior RTL Design Engineer

Texas Instruments; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Texas Instruments in Bengaluru seeks an experienced RTL Design Engineer to drive front-end design for multi-clock-domain blocks in custom ICs. You will partner with systems, analog design, verification, and test teams from concept to market release, participating in design reviews and documentation.

The role emphasizes Verilog RTL, lint, simulation, timing constraints, and DFT awareness, with opportunities to optimize area, power, and performance while collaborating across time zones.

Qualifications

• Front-end design experience for multi-clock-domain blocks.
• Translate system requirements into micro-architectures and RTL.
• Ability to read sparse legacy docs and infer functionality.

Responsibilities

• Define or enhance the micro-architecture for digital blocks/topology.
• RTL development and verification (RTL and Gate level).
• Collaborate with analog designers on mixed-signal/DSP blocks and interfaces.
• Work with verification team on full-chip verification plans and RCAs.
• Support silicon validation, test program development, and customer debug needs.
• Drive architectural optimization for area, power and performance.

Skills

RTL design

Verilog

Timing constraints

DFT awareness

Micro-architecture

Debug & verification

Education

Bachelors / Masters in Electrical / Electronics Engineering

Tools

Cadence toolchain

Job description

If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!

The Custom product business is delivering industry leading custom IC system solutions including display and touch power products, camera PMICs, charger power products, power switches/muxes, Laser drivers, High speed communication interfaces. Our solutions integrate signal chain and power components, that enable TI customers to differentiate their next-gen products in the personal electronics domain. This is a great opportunity to be part of the best custom semiconductor team in the world.

What will you be doing in this role? (Responsibilities)

• Be a key team member from product definition till release to market, working closely with all functions (e.g. systems, analog design, verification, test, applications).
• Define or enhance the micro-architecture for digital blocks/top and designing them along with rest of the team.
• RTL development and verification (RTL and Gate level).
• Collaborate with analog designers on mixed-signal and DSP blocks and interfaces.
• Work closely with verification team to build the full-chip verification plan, tests. Support functional debugs and RCAs.
• Support silicon validation activities, test program development and the customer engagement and silicon/application debug needs.
• Drive architectural optimization for area, power and performance improvements for a given node.
• Address performance bottlenecks through micro-architecture.

What do we expect from you? (Mini Qualifications)

• Hands on front-end design experience of complex multi clock domain blocks.
• Ability to convert high level system requirements/changes into micro-architectural changes and then into RTL
• Ability to extract the functionality / micro-architecture of existing design even with sparse legacy documentation
• Familiarity with verification environments to be able to actively participate in functional debugs
• Good knowledge on static timing analysis and constraints debugging.
• Understand and own in detail the functional specifications of the IPs/SoC
• Ensure that design-for-test (DFT) standards are addressed by design
• Participate in and conduct design reviews. Create the necessary design documentation
• Ability to take initiatives and drive the results working with team members across time-zones
• Handling & owning design deliverables and schedule
• Bachelors / Masters in Electrical / Electronics Engineering

Preferred Skills/ Experience

• 2-5years of relevant experience
• Excellent RTL design (Verilog) skill including Lint, Simulation, Debug, Synthesis and LEC (preferably Cadence toolchain).
• Experience in identifying and implementing complex ECO in netlist.
• Experience in writing and debugging timing constraints at IP / SoC level
• Experience in silicon functional debug/RCA to map bugs to RTL. Familiarity with Si-bringup & Bench testing
• Experience in FPGA prototyping of full/parts of system would be a plus.
• Experience in digital signal processing and Matlab modeling would be a plus.