RTL Design Engineer - SoC

Cyient; Hyderabad; On-site; INR 1,800,000 - 2,500,000; Full time

Job summary

Cyient Hyderabad is seeking an experienced ASIC/SoC Design Engineer with 6-9 years to contribute to architecture, logic, physical design, verification, fabrication and packaging of chips. You will work on RTL coding and hands-on SoC integration, including experience with ARM-based cores.

Strong knowledge of Verilog/SystemVerilog, basic verification, memory controllers, timing, and synthesis is required. Experience with high-speed peripherals (PCIe, USB) and UPF power-domain design is a plus.

Qualifications

• Experience: 6-9 years in ASIC/SoC design and development.
• Good knowledge of digital concepts and ASIC flow.
• Hands-on RTL coding experience.
• Hands-on SoC design and integration experience.
• Worked on ARM-based SoCs.
• Peripherals including PCIe and USB.
• Developing UPF with multiple power domains and power-aware simulations.
• Verilog/SystemVerilog is a must.
• Basic verification knowledge (functions and tasks).
• Understanding of memory controller designs.
• Experience in synthesis and timing concepts.

Responsibilities

• Under direct supervision, performs engineering work and applied research in IC design.
• Work includes architectural design, logic design, circuit design, physical design, verification, fabrication, and packaging.

Skills

RTL coding

SoC design

ARM SoCs

PCIe/USB peripherals

Verilog/SystemVerilog

UPF power-aware design

Memory controller concepts

Synthesis & timing concepts

Tools

UPF

Job description

• Experience: 6-9 years.
• Good knowledge on the digital concepts and ASIC flow
• Experience in RTL coding
• Must have hands on experience with SoC design and integration.
• The candidate worked on ARM SoCs
• Peripherals including high speed ones like PCIe, USB
• Developing UPF with multiple power domains, including conducting UPF checks and power aware simulations
• Experience in Verilog/System-Verilog is a must.
• Basic knowledge on verification , functions and tasks
• Understanding of Memory controller designs
• Must have experience in Synthesis / Understanding of timing concepts

Roles and Responsibilities

Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.