Soc Design Lead

MediaTek; Bengaluru; On-site; INR 3,500,000 - 11,000,000; Full time

Job summary

MediaTek in Bengaluru is seeking a Design Lead to drive end-to-end RTL design of SoCs and IP blocks, guiding microarchitecture definition and verification from concept to tape-out.

You will lead a team of digital engineers, balance PPA, collaborate with architecture, verification and physical design, and resolve complex bugs to ensure successful silicon delivery.

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 15 to 20 years of relevant RTL design experience.
• Proven track record of technical leadership and management capacity.

Responsibilities

• Execution & Delivery: Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet the Performance, Area, Power and Schedule targets.
• Team Leadership: Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.
• PPA Optimization: Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.
• Cross-Functional Collaboration: Partner with architecture, verification, and physical design teams.
• Sign-off & Debug: Drive resolution on complex bugs, logic issues, and sign-off checks.

Skills

RTL design

Leadership

PPA optimization

Cross-functional

Sign-off & debugging

STA/CDC/LEC

Education

Bachelor's or Master's in Electrical/Electronics/Computer Engineering

Tools

Verilog

SystemVerilog

Python

Perl

ARM

RISC-V

PCIe

USB

DDR

Job description

Design Lead works with hardware engineering teams to build complex chips, System-on-Chips (SoCs), and IP/Sub-system blocks.

Guides microarchitecture definition, RTL design, verification, and physical implementation from conception through tape-out, balancing power, performance, area, and schedule goals.

Key Responsibilities

• Execution & Delivery: Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet the Performance, Area, Power and Schedule targets.
• Team Leadership: Manage, mentor, and set goals for a team of digital engineers involved in design, synthesis, and timing.
• PPA Optimization: Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics.
• Cross-Functional Collaboration: Partner with architecture, verification, and physical design teams.
• Sign-off & Debug: Drive resolution on complex bugs, logic issues, and sign-off checks.

Requirements & Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 15 to 20 years of relevant RTL design experience.
• Proven track record of technical leadership and management capacity.

Core Technical Skills

• Design Languages: Advanced proficiency in Verilog, System-Verilog, and scripting tools like Python or Perl.
• Architecture Knowledge: Familiarity with ARM or RISC‑V processors, bus protocols (AXI/AHB), and high‑speed interfaces (PCIe, USB, DDR).
• Sign-off Methodologies: Experience with Static Timing Analysis (STA), Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).