RTL Design Leader

STMicroelectronics; Dadri; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

STMicroelectronics is seeking a Chip Lead / SoC Design Leader in Dadri, India, to oversee the SoC design and development while ensuring high quality products on schedule. The role requires extensive experience in SoC architecture and a strong educational background in Electronics/Electrical Engineering.

Candidates must demonstrate effective communication, strong leadership skills, and the ability to mentor technical teams. Successful applicants will work closely with multi-disciplinary teams, driving specifications and managing project schedules.

Qualifications

• Extensive experience with SoC architecture, micro-architecture, and full-chip design across 28 nm, 16 FFC, 7 nm nodes.
• Solid knowledge of RTL design, asynchronous clock domains, timing analysis, and DFT.
• Experience with pre-Si validation, post-Si validation, and test and product engineering.

Responsibilities

• Drive architecture and application teams to converge on optimal specifications balancing performance, power, cost, and PPA.
• Engage systems teams to ensure design decisions meet system level requirements.
• Conduct feasibility, risk, power, and die size analyses.

Skills

SoC architecture

RTL design

Power management

High-speed SerDes

Education

Bachelor’s or Master’s degree in Electronics/Electrical Engineering

Tools

ARM real-time cores

AHB/AXI

Arteris NOC

Job description

Role

Chip Lead / SoC Design Leader

Job Description

Lead the SoC design and development across technology nodes, driving architecture, specifications, RTL implementation, verification, and integration from concept to silicon. Work closely with systems, analog, foundational IP, packaging, validation, marketing, and external vendors to deliver high quality products on schedule.

Responsibilities

• Drive architecture and application teams to converge on optimal specifications balancing performance, power, cost, and PPA.
• Engage systems teams and client interfaces to ensure design decisions meet system level requirements.
• Lead technical discussions on IP selection, SoC architecture, clocking, power management, interconnect, and memory subsystems.
• Conduct feasibility, risk, power, and die size analyses.
• Oversee RTL development, top‑level integration, verification, DFT, and physical implementation through the entire RTL‑to‑GDS flow.
• Run weekly reviews of open issues, monitor progress, and provide technical leadership for cross‑functional teams.
• Manage project schedules, status reporting, and reviews in compliance with the product development lifecycle.
• Collaborate with engineering, validation, packaging, quality & reliability, and marketing teams.

Technical Skills / Background

• Bachelor’s or Master’s degree in Electronics/Electrical Engineering.
• Extensive experience with SoC architecture, micro‑architecture, and full‑chip design across 28 nm, 16 FFC, 7 nm nodes.
• Proficiency in advanced ARM real‑time and application cores, memory subsystems, AHB/AXI, Arteris NOC, high‑speed SerDes, debugging, and clock/reset/power management.
• Solid knowledge of RTL design, asynchronous clock domains, timing analysis, and DFT.
• Experience with pre‑Si validation, post‑Si validation, and test and product engineering.
• Understanding of automotive functional safety ISO 26262 is a plus.

Leadership Skills

• Proven track record managing complex, large‑scale designs and coordinating multi‑disciplinary teams.
• Strong negotiation, conflict‑resolution, and interpersonal skills.
• Effective communication with management and technical sub‑groups.
• Ability to mentor and provide direction to small‑to‑medium technical teams.

Equal Opportunity & Diversity Statement

ST is committed to fostering a diverse and inclusive workplace, actively rejects discrimination, and offers equitable career development and opportunities. All candidates are encouraged to apply regardless of meeting every single requirement.