RTL Engineer

118-WW TMG MFG OPS; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

118-WW TMG MFG OPS is seeking an experienced RTL Design Engineer to drive architecture for high‑performance MCUs and connected devices. You will own RTL coding, testbenches, and cross‑functional verification, while mentoring junior engineers in a fast-paced MCU organization.

Ideal candidates bring 5+ years in RTL design, strong SystemVerilog/VHDL skills, and deep knowledge of timing closure, power optimization, and workflow automation. Bengaluru-based role with global collaboration.

Qualifications

• B.S. or M.S. in Electrical/Electronics/CS or related discipline.
• 5+ years hands-on RTL design on high-performance SoCs, MCUs, or wireless devices.
• Proficiency in SystemVerilog or VHDL, with clean, synthesizable RTL.

Responsibilities

• Define and implement RTL architecture for complex SoCs.
• Develop and maintain synthesizable SystemVerilog/VHDL code for digital blocks.
• Create and own RTL simulation and synthesis testbenches and regression tests.
• Collaborate with verification engineers to ensure coverage and bug resolution.
• Perform timing analysis and constraint development (SDC) to hit timing/power targets.
• Lead power-aware design techniques (clock gating, DVFS) and LP specs.
• Participate in design reviews with clear documentation of decisions.
• Improve RTL quality through coding guidelines and linting.
• Mentor junior RTL designers and promote knowledge sharing.
• Coordinate with EDA team to integrate new tools and flows.
• Support post-silicon bring-up and RTL-related performance tuning.

Skills

RTL design experience

SystemVerilog/VHDL

Digital design fundamentals

Synthesis & STA

UVM & verification

Scripting (tcl/perl/python)

Leadership & mentoring

CI/CD flow automation

Education

B.S./M.S. in Electrical/Electronics/CS

Tools

DC

Design Compiler

Innovus

Job description

We are at a pivotal moment where technology is rapidly evolving, and we have some exciting opportunities within our MCU organization that place us right at the center of this transformation.

Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting‑edge technologies with real-world impact.

Minimum requirements:

• B.S. (or M.S.) in Electrical/Electronics/Computer Engineering or related discipline.
• 5+years of hands‑on RTL design experience on high‑performance SoCs, preferably MCUs or wireless connectivity devices.
• Strong proficiency in SystemVerilog or VHDL; demonstrated ability to write clean, synthesizable, and testable RTL.
• Deep understanding of digital design fundamentals: pipelining, state‑machine design, bus protocols (AHB/APB/AXI), FIFO, arbitration, and clock domain crossing.
• Experience with synthesis tools (DC, Design Compiler, Innovus) and static timing analysis; ability to meet tight performance and power targets.
• Proven track record in low‑power RTL techniques (clock gating, power‑domain isolation, dynamic voltage/frequency scaling).
• Familiarity with verification flow (UVM, simulation, coverage) to effectively collaborate with DV teams.
• Advanced scripting/automation skills (tcl, perl, python, Bash) for flow automation and CI/CD pipelines.
• Excellent written and verbal communication; strong stakeholder‑management skills across global functional teams.
• Demonstrated ability to lead design efforts, meet aggressive schedule milestones, and mentor junior engineers.

Preferred qualifications:

• Define and implement RTL architecture for complex SoCs, selecting appropriate coding styles, clocking strategies, and low‑power techniques.
• Develop and maintain synthesizable SystemVerilog/VHDL code for digital blocks (core, peripherals, interfaces, DMA, etc.).
• Create and own RTL simulation and synthesis testbenches, running regression to verify functional correctness and timing closure.
• Collaborate with verification engineers to ensure comprehensive test coverage, resolve RTL bugs, and support pre‑silicon validation.
• Perform timing analysis, constraint development (SDC), and STA, iterating on RTL to meet clock‑frequency, setup/hold, and power budgets.
• Lead power‑aware design techniques (clock gating, power domains, voltage scaling) and ensure compliance with low‑power specifications.
• Participate in design reviews, providing clear documentation of design decisions, trade‑offs, and risk assessments.
• Drive RTL quality improvement by establishing coding guidelines, linting policies, and best‑practice checklists.
• Mentor junior RTL designers, fostering a culture of code quality, continuous learning, and knowledge sharing.
• Work with the EDA team to evaluate and integrate new synthesis, place‑and‑route, and static timing tools, improving flow efficiency.
• Support post‑silicon bring‑up and bring‑down activities, assisting software/ROM teams with RTL‑related debug and performance tuning.