Principal DFT Engineers

NXP Semiconductors; Maharashtra; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

NXP Semiconductors in Pune, India is seeking a senior DFT lead to architect and implement DFT strategies for complex SOCs. You will oversee DFT instrument insertion, verification coverage, and coordination with DV, BE, and test teams to bring up silicon test patterns.

Candidates should have 12+ years in DFT with hands-on experience using Mentor/Synopsys tools, strong JTAG/ATPG knowledge, and a proven track record leading DFT efforts in production environments.

Qualifications

• BE/MS in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.
• Hands-on with Mentor/Synopsys test generation tools for large complex designs.
• DFT lead for complex SOC TO and production.
• Strong knowledge of DFT techniques: JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500, MBIST, LBIST, SSN.

Responsibilities

• Architect DFT design and define implementation strategies.
• Instruct and guide Jr. DFT Engineers and coordinate with DV, SOC, and BE teams.
• Collaborate with physical design to close timing in DFT mode.
• Sign-off on DFT requirements and verification coverage.
• Create or oversee generation of test vectors.
• Work with test engineers to bring up test patterns on silicon.

Skills

DFT leadership

Mentor/Synopsys tools

JTAG

ATPG

MBIST

LBIST

SSN

Test pattern translation

Education

BE/MS degree in Electronics/Electrical/Computer Engineering

Tools

Mentor/Synopsys test generation tools

Job description

Responsibilities

• As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr. DFT Engineers.
• Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.
• Create test vectors or oversee their creation.
• Collaborate with physical design team to close timing in DFT mode.
• Sign-off DFT requirements are being met.
• Work with testing team to bring-up test patterns on silicon.

Requirements

• Minimum Qualifications
• BE/MS degree in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.
• Hands-on expertise with Mentor/Synopsys test generation tools for large complex designs.
• DFT lead experience for complex SOC TO and Production.
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST, SSN.

Preferred Qualifications

• Experience with synthesis, STA and back-end implementation flows.
• Familiar with Tessent shell flow for DFT instruments insertion include MBIST, IJTAG, SSN, BSCAN, OCC etc.
• Solid Lab and test floor bring-up and debug experience.
• Yield estimation and test optimization.
• DFT AI mindset.

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