Location : Bangalore, Modeofwork:WFO(5days)
Salary : Best in the industry
Key Responsibilities
SoC DFT Architecture & Implementation
- Contribute to SoC-level DFT architecture for custom and platform-based SoCs.
- Implement DFT plans across one or more concurrent SoC programs.
- Execute DFT deliverables in alignment with project schedules and quality targets.
Execution & Technical Ownership
- Perform DFT RTL integration, scan insertion, and test architecture implementation.
- Implement and support:
- Scan, Compression, and ATPG flows
- MBIST, BISR, and redundancy schemes
- JTAG / TAP, Boundary Scan, and debug infrastructure
- Ensure DFT readiness across functional, scan, and low-power modes.
- Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and implementation.
- Execute ATPG pattern generation, simulation, and debug to achieve target test coverage and quality.
Cross-Functional & Manufacturing Interface
- Work closely with physical design teams to support scan and test logic closure with minimal PPA impact.
- Interface with manufacturing, ATE, and OSAT teams on test requirements, vector delivery, and silicon bring-up activities.
- Support post-silicon debug, yield ramp, and test optimization efforts.
- Participate in customer-facing technical discussions related to DFT implementation and execution.
Methodology & Execution Support
- Follow established DFT methodologies, flows, and checklists across Semifive programs.
- Contribute to automation, scripting, and reuse to improve DFT efficiency and execution quality.
- Support DFT signoff activities, including review of reports and tapeout readiness deliverables.
Qualifications
- B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.
- 4–12 years of experience in DFT implementation for complex SoCs.
- Hands-on experience in executing DFT implementation for one or more SoC tapeouts.
- Strong expertise in:
- Scan, Compression, and ATPG methodologies
- MBIST, BISR, and memory repair schemes
- JTAG / TAP and Boundary Scan
- DFT RTL integration and pattern simulation
- Hands-on experience with industry-standard DFT tools, such as:
- Siemens Tessent
- Synopsys DFTMAX / TestMAX
- SpyGlass DFT (or equivalent)
- Good understanding of:
- Low-power DFT challenges (UPF/CPF)
- Scan and test-mode timing closure
- Physical implementation constraints for DFT
- Experience working with manufacturing, ATE, and post-silicon validation teams.
- Good problem-solving and communication skills with the ability to work in cross-functional teams.