Sr. DFT Engineer

Kinara.ai; Pune District; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Kinara.ai is seeking a Senior DFT Engineer to design, implement, and verify DFT architectures for complex SoCs, ensuring robust testability and high-quality silicon. You will collaborate with RTL, physical design, and verification teams to insert DFT and optimize test efficiency.

The role requires hands-on experience with ATPG tools, UPF/CPF-based low-power DFT, and familiarity with fault models, memory/logic BIST, and ATE bring-up.

Qualifications

• Experience with DFT methodologies including scan, MBIST, LBIST, and JTAG.
• Hands-on experience with industry standard ATPG tools.
• Proficiency in UPF/CPF-based low-power DFT.
• Knowledge of fault models (stuck-at, transition, path delay).
• Familiarity with physical design constraints for DFT.
• Experience in silicon debug and ATE bring-up.

Responsibilities

• Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST and logic BIST strategies.
• Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• Perform DFT verification at RTL and gate-level simulations.
• Work with ATE teams for test program development and silicon bring-up.
• Optimize test coverage, pattern count, and test time.

Skills

DFT methods

ATPG tools

UPF/CPF DFT

Fault models

Physical design constraints

Silicon debug

Education

BE/BTech in EEE

Tools

ATPG Tools

UPF/CPF Tools

Job description

Senior DFT Engineer: You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon.

Key Responsibilities

• Define and implement DFT architecture for SoCs (scan, MBIST, LBIST, boundary scan).
• Develop and integrate scan insertion, test compression, and ATPG patterns.
• Implement memory BIST and logic BIST strategies.
• Collaborate with RTL and physical design teams for DFT insertion and timing closure.
• Perform DFT verification at RTL and gate-level simulations.
• Work with ATE teams for test program development and silicon bring-up.
• Optimize test coverage, pattern count, and test time.

Required Skills

• Strong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG.
• Hands-on experience with industry standard ATPG tools.
• Proficiency in UPF/CPF-based low-power DFT.
• Knowledge of fault models (stuck-at, transition, path delay).
• Familiarity with physical design constraints for DFT.
• Experience in silicon debug and ATE bring-up.

Preferred Qualifications

• Pas experience with SoC level DFT
• Exposure to high-speed interfaces and DFT for mixed-signal blocks.
• Strong problem-solving and communication skills.

Education

• Bachelor s or Master s in Electrical/Electronics Engineering.

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