Senior Principal DFT Engineer

NXP Semiconductors; Maharashtra; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

NXP Semiconductors in Pune seeks a DFT Lead with over 12 years of experience in DFT design and strong knowledge of JTAG and ATPG techniques. The role involves architecting DFT design, collaborating with IP designers, and overseeing test patterns on silicon. Candidates should have hands-on expertise with test generation tools and a BE/MS degree in Electronics/Electrical/Computer Engineering. This is a vital role requiring solid DFT leadership capabilities and methodologies implementation.

Qualifications

• Minimum 12+ years of DFT experience required.
• Hands-on expertise with tools for large complex designs expected.
• Experience leading DFT for complex SOC TO and Production.

Responsibilities

• Architect and lead DFT design, including instrument insertion and simulation.
• Define and implement DFT structures, methodologies, and testing.
• Collaborate with testing team for silicon test pattern bring-up.

Skills

DFT design architecture

Mentor/Synopsys test generation tools

JTAG

ATPG

yield estimation

test optimization

Education

BE/MS degree in Electronics/Electrical/Computer Engineering

Tools

Tessent shell flow

Job description

Responsibilities

• As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr. DFT Engineers.
• Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.
• Create test vectors or oversee their creation.
• Collaborate with physical design team to close timing in DFT mode.
• Sign-off DFT requirements are being met.
• Work with testing team to bring-up test patterns on silicon.

Requirements

• Minimum Qualifications
• BE/MS degree in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.
• Hands-on expertise with Mentor/Synopsys test generation tools for large complex designs.
• DFT lead experience for complex SOC TO and Production.
• Strong fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST, SSN.

Preferred Qualifications

• Experience with synthesis, STA and back-end implementation flows.
• Familiar with Tessent shell flow for DFT instruments insertion include MBIST, IJTAG, SSN, BSCAN, OCC etc.
• Solid Lab and test floor bring-up and debug experience.
• Yield estimation and test optimization.
• DFT AI mindset.