Principal DFT Engineer

NXP Semiconductors; Maharashtra; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

NXP Semiconductors in Pune seeks a senior DFT Lead to architect and implement DFT designs for SOCs, manage DFT instrumentation and simulations, and ensure coverage with DV and BE teams. You will guide junior engineers and collaborate with SOC leads to meet timing and test requirements, delivering robust DFT solutions on silicon.

Candidate should have 12+ years in DFT with hands-on experience using Mentor/Synopsys tools and Tessent, and a strong understanding of JTAG, ATPG, MBIST, LBIST and

Qualifications

• BE/MS degree in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.
• Hands‑on expertise with Mentor/Synopsys test generation tools for large complex designs.
• DFT lead experience for complex SOC TO and Production.
• Strong knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500, MBIST, LBIST, SSN.

Responsibilities

• As a Pune MCU team DFT lead, architect DFT design, lead DFT instruments insertion and simulation; collaborate with SOC leads/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; coordinate with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; guide Jr. DFT Engineers.
• Define and implement DFT structure, design and methodologies including scan/mbist/jtag and functional testing.
• Create test vectors or oversee their creation.
• Collaborate with physical design team to close timing in DFT mode.
• Sign-off DFT requirements are met.
• Work with testing team to bring-up test patterns on silicon.

Skills

DFT concepts

Testing methodologies

Leadership

Cross-functional collaboration

Education

BE in Electronics/Electrical/Computer Engineering

MS in relevant field (preferred)

Tools

Mentor tools

Synopsys tools

Tessent

Job description

• As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr. DFT Engineers.
• Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.
• Create test vectors or oversee their creation.
• Collaborate with physical design team to close timing in DFT mode.
• Sign-off DFT requirements are being met.
• Work with testing team to bring-up test patterns on silicon.

Responsibilities

• As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and review verification coverage; work with BE lead for DFT modes STA, IR drop analysis; work with test engineers to bring up test patterns on silicon; provide guidance to Jr. DFT Engineers.
• Define and implement DFT structure, design and methodologies that include scan/mbist/jtag and functional testing.
• Create test vectors or oversee their creation.
• Collaborate with physical design team to close timing in DFT mode.
• Sign-off DFT requirements are being met.
• Work with testing team to bring-up test patterns on silicon.

Requirements

• Minimum Qualifications
• BE/MS degree in Electronics/Electrical/Computer Engineering with 12+ years of DFT experience.
• Hands‑on expertise with Mentor/Synopsys test generation tools for large complex designs.
• DFT lead experience for complex SOC TO and Production.
• Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST, LBIST, SSN.

Preferred Qualifications

• Experience with synthesis, STA and back‑end implementation flows.
• Familiar with Tessent shell flow for DFT instruments insertion include MBIST, IJTAG, SSN, BSCAN, OCC etc.
• Solid Lab and test floor bring‑up and debug experience.
• Yield estimation and test optimization.
• DFT AI mindset.

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