DFT Engineer

Wenger & Watson; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Wenger & Watson in Bengaluru seeks an experienced DFT Architect/Principal DFT Engineer to drive DFT architecture and implementation for next‑generation high‑performance SoCs and IPs.

Responsibilities include end‑to‑end DFT strategy, Scan/ATPG, MBIST/LBIST, JTAG/IJTAG, and IEEE 1500, plus optimizing test time and cost while collaborating with RTL, Architecture, and Product/Test teams.

Qualifications

• 7+ years in DFT design, architecture and verification.
• Strong expertise in ATPG and advanced fault models.
• Experience with MBIST and LBIST implementations.
• Proficiency in hierarchical DFT and core-wrapper methods.
• Hands-on with major EDA tools (TestMax/TetraMAX, Tessent, Modus).
• Solid understanding of STA and DFT timing closure.
• Scripting skills in Tcl, Perl, Python or Shell.

Responsibilities

• Define end-to-end DFT architecture and test strategy for complex SoCs.
• Lead Scan/ATPG, MBIST, LBIST, JTAG, IJTAG and IEEE 1500 implementations.
• Drive hierarchical DFT integration, test-mode clocking and power-aware test methods.
• Optimize test time, data volume and manufacturing cost.
• Collaborate with RTL, Architecture, and Product/Test Eng teams.
• Lead DFT verification, post-silicon bring-up and ATE validation.
• Evaluate and establish DFT flows using leading EDA tools.

Skills

DFT design

Architecture

Verification

ATPG & faults

MBIST/LBIST

Hierarchical DFT

Scripting (Tcl/Python)

Tools

Synopsys TestMax/TetraMAX

Siemens Tessent

Cadence Modus

Job description

Hiring: DFT Architect / Principal DFT Engineer

Locations: Bangalore

Experience: 7+ years

We are looking for experienced DFT Architects / Principal DFT Engineers to drive DFT architecture, methodology, and implementation for next-generation high-performance SoCs and IPs.

Key Responsibilities

• Define end-to-end DFT architecture and test strategy for complex SoCs
• Lead Scan/ATPG, MBIST, LBIST, JTAG, IJTAG and IEEE 1500 implementations
• Drive hierarchical DFT integration, test-mode clocking and power-aware test methodologies
• Optimize test time, test data volume and manufacturing cost
• Collaborate with RTL, Architecture, Physical Design and Product/Test Engineering teams
• Lead DFT verification, post-silicon bring-up, ATE validation and failure analysis
• Evaluate and establish DFT flows using leading EDA tools

Must-Have Skills

• 10–15+ years of hands‑on DFT design, architecture and verification
• Strong expertise in ATPG and advanced fault models
• Experience with MBIST/BISR and LBIST
• Expertise in hierarchical DFT and core-wrapper methodologies
• Proficiency with Synopsys TestMax/TetraMAX, Siemens Tessent or Cadence Modus
• Strong understanding of STA and DFT timing closure
• Strong scripting skills in Tcl / Perl / Python / Shell