Physical Design (PD) – Memory Compiler Engineer | Logicsemi Technologies | Hyderabad

Logicsemi Technologies Pvt Ltd.; Hyderabad; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Logicsemi Technologies Pvt Ltd. in Hyderabad, India, seeks a seasoned Physical Design - Memory Compiler Engineer to own memory compiler characterization, physical implementation, timing closure and verification, and to drive high-density memory macros with optimum PPA.

You will lead block-level floorplanning, place & route, DRC/LVS, CTS, and STA, collaborate with memory design, ASIC, DFT teams, and participate in F2F interviews in Hyderabad, ensuring robust tapeouts and comprehensive

Qualifications

• Bachelor's or Master's in Electrical Engineering, Electronics & Communication, VLSI Design or related field.
• Minimum 4+ years of ASIC physical design and memory compiler experience.
• Hands-on expertise with EDA tools: IC Compiler/Fusion, Innovus, PrimeTime, Calibre.
• Deep memory compiler flows, characterization, and custom macro integration.
• Strong power, IR drop, and signal integrity understanding; able to drive PPA improvements.

Responsibilities

• Architect, configure and execute memory compiler and macro integration flows.
• Perform block-level floorplanning, pin placement, power grid planning and P&R.
• Execute STA, CTS, and timing closure for memory macros.
• Conduct DRC/LVS/ERC checks and physical verification.
• Collaborate with memory design, ASIC, and tapeout teams to optimize PPA.
• Participate in F2F technical interviews in Hyderabad and provide implementation reports.

Skills

Memory compilers

Physical design

P&R tools

Innovus

PrimeTime

Calibre

Memory macros

Power integrity

Python/Tcl

Cross-functional

Education

Bachelor's or Master's in Electrical Engineering / ECE / VLSI Design

Tools

Synopsys IC Compiler

Fusion Compiler

Cadence Innovus

PrimeTime

Calibre

Job description

Position Summary:

Driving advanced semiconductor physical design, memory compiler generation, and ultra-deep submicron ASIC implementation in Hyderabad, Logicsemi Technologies is actively seeking an accomplished Physical Design (PD) - Memory Compiler Engineer for a permanent professional engagement. In this vital VLSI implementation role, you will architect, optimize, and verify high-density memory compilers, custom memory instances, and block-level physical designs, ensuring uncompromised power, performance, and area (PPA) metrics. Bringing 4+ years of progressive professional experience in physical design and memory compiler flows, you will empower global semiconductor innovators to achieve market-leading chip performance. This prestigious career opportunity offers competitive remuneration, high technical visibility, and exceptional professional growth within a premier semiconductor solutions enterprise.

Detailed Job Description:

As a Physical Design (PD) - Memory Compiler Engineer supporting Logicsemi Technologies in Hyderabad, India, you will take full operational, architectural, and tactical ownership of memory compiler characterization, physical implementation, timing closure, and physical verification. Your day-to-day responsibilities include integrating memory compilers into top-level floorplans, performing place and route (P&R), executing static timing analysis (STA), running DRC/LVS physical verification, and participating in mandatory Face-to-Face (F2F) technical interviews in Hyderabad. You will collaborate closely with cross-functional circuit design, memory compiler development, and tapeout squads.

Key Responsibilities:

• Architect, configure, and execute physical design and implementation flows specifically tailored for memory compilers and embedded memory macros.
• Perform block-level floorplanning, pin placement, power grid planning, and hierarchical place and route (P&R).
• Execute rigorous static timing analysis (STA), constraint validation, clock tree synthesis (CTS), and timing closure for memory macros.
• Conduct physical verification checks including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and electrical rule checks (ERC).
• Collaborate with memory design teams to optimize power, performance, and area (PPA) metrics across advanced process nodes.
• Collaborate seamlessly with cross-functional ASIC design, DFT, and physical verification squads.
• Participate in mandatory Face-to-Face (F2F) technical interview evaluations and engineering reviews in Hyderabad.
• Maintain comprehensive implementation reports, timing sign-off checklists, and tapeout runbooks.

Required Qualifications & Skills:

• Bachelor's or Master's degree in Electrical Engineering, Electronics and Communication, VLSI Design, or related discipline.
• Minimum of 4+ years of progressive professional experience in ASIC physical design and memory compiler implementation.
• Strong, demonstrable hands‑on professional expertise in physical design EDA tools (Synopsys IC Compiler / Fusion Compiler, Cadence Innovus).
• Comprehensive working knowledge and practical proficiency in static timing analysis (Synopsys PrimeTime) and physical verification (Calibre).
• Deep practical experience with memory compiler flows, memory characterization, and custom macro integration.
• Solid practical grasp of advanced power grid design, electromigration, IR drop analysis, and signal integrity.
• Proven analytical, troubleshooting, and cross-functional communication capabilities.
• Mandatory availability for a Face-to-Face (F2F) technical interview process in Hyderabad, India.

Nice-to-Have Skills:

• Professional training or certifications in advanced VLSI physical design and deep submicron ASIC sign-off methodologies.
• Prior professional working experience in top‑tier semiconductor product companies, foundries, or memory IP development houses.
• Hands‑on familiarity with scripting languages like Python, Tcl, or Perl for physical design automation.
• Experience utilizing enterprise project management and ticketing platforms such as Jira and Confluence.
• Exposure to FinFET technology nodes and multi‑VDD power management architectures.

Application Information:

• Recruiter: Logicsemi Technologies Recruitment Division
• Contact Name: Lakshmi L (HR Executive)
• Email: [e-mail]
• Phone:
• Company Website: https://www.logic-semi.com
• Salary/Rate: Market Competitive / Enterprise Semiconductor Package
• Deadline: Open until filled (Urgent Hyderabad Memory Compiler PD Opening)
• Notice Period: Immediate to 30 Days Preferred
• Contract Duration: Permanent / Full-Time Engagement (Hyderabad)

Recruitment Pro Tip:

When applying for this Physical Design (PD) - Memory Compiler Engineer position through Logicsemi Technologies, ensure your resume explicitly highlights your memory compiler integration portfolio, P&R tool proficiency, and confirmation of your availability for an F2F interview in Hyderabad.