Analog Layout Engineer | Logicsemi Technologies | Hyderabad

Logicsemi Technologies Pvt Ltd.; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Logicsemi Technologies Pvt Ltd in Hyderabad, India is seeking an experienced Analog Layout Engineer to design and verify analog and mixed-signal ICs for advanced process nodes, including TSMC 3nm.

You will own transistor‑level layout, floorplanning, parasitic extraction, LVS/DRC checks, and collaborate with cross‑functional teams, with face‑to‑face interviews in Hyderabad.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics and Communication, VLSI Design, or related discipline.
• Minimum of 4+ years of progressive professional experience in analog and mixed-signal layout design within the semiconductor industry.
• Strong, demonstrable hands‑on professional expertise in custom layout tools (Cadence Virtuoso, Calibre, Hercules).
• Comprehensive working knowledge and practical proficiency in advanced node physical verification (DRC/LVS/PERC).
• Deep practical experience with TSMC advanced process nodes, specifically mandatory hands‑on TSMC 3nm process experience.
• Solid practical grasp of analog matching, noise reduction, shielding, and high‑frequency layout parasitics.
• Proven analytical, troubleshooting, and cross‑functional communication capabilities.
• Mandatory availability for a Face‑to‑Face (F2F) technical interview process in Hyderabad, India.

Responsibilities

• Design and execute custom transistor-level analog and mixed-signal layouts across advanced semiconductor process nodes.
• Perform comprehensive floorplanning, device matching, shielding, guard-ring placement, and parasitic resistance/capacitance minimization.
• Execute rigorous physical verification including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and antenna checks.
• Partner with circuit designers to analyze post-layout simulation results and implement layout iterations for optimal performance.
• Specialize in advanced process node tapeouts, specifically leveraging TSMC 3nm process experience and design rules.
• Collaborate seamlessly with cross-functional design verification, physical design, and manufacturing operations squads.
• Ensure strict adherence to electromigration, IR drop, ESD protection, and DFM (Design for Manufacturing) standards.
• Maintain comprehensive layout documentation, DRC waiver logs, and tapeout checklist execution reports.

Skills

Cadence Virtuoso

Calibre

Hercules

Education

Bachelor’s or Master’s in Electrical Engineering, Electronics and Communication, VLSI Design

Tools

DRC/LVS/PERC

Job description

Position Summary:

Driving advanced semiconductor physical design, ultra-deep submicron layout engineering, and TSMC advanced process node customization in Hyderabad, Logicsemi Technologies is actively seeking an accomplished Analog Layout Engineer for a permanent professional engagement. In this vital VLSI engineering role, you will architect, design, and verify high-performance analog and mixed-signal integrated circuits, ensuring uncompromised matching, signal integrity, and manufacturability on cutting-edge process nodes. Bringing 4+ years of progressive professional experience in analog layout design and TSMC process familiarity, you will empower global semiconductor innovators to achieve market-leading chip performance. This prestigious career opportunity offers competitive remuneration, high technical visibility, and exceptional professional growth within a premier semiconductor solutions enterprise.

Detailed Job Description:

As an Analog Layout Engineer supporting Logicsemi Technologies in Hyderabad, India, you will take full operational, architectural, and tactical ownership of transistor-level layout, floorplanning, parasitic extraction, and physical verification. Your day-to-day responsibilities include designing custom analog blocks (such as PLLs, ADCs, DACs, bandgaps, and LDOs), executing LVS/DRC verification checks, managing advanced matching techniques, and working directly with TSMC 3nm process nodes. You will participate in mandatory Face-to-Face (F2F) technical interviews in Hyderabad while collaborating closely with cross-functional circuit design, physical verification, and tapeout squads. Furthermore, you will manage application requirements by submitting your updated resume via direct email to Lakshmi L at [e-mail].

Key Responsibilities:

• Design and execute custom transistor-level analog and mixed-signal layouts across advanced semiconductor process nodes.
• Perform comprehensive floorplanning, device matching, shielding, guard-ring placement, and parasitic resistance/capacitance minimization.
• Execute rigorous physical verification including Design Rule Checking (DRC), Layout Versus Schematic (LVS), and antenna checks.
• Partner with circuit designers to analyze post-layout simulation results and implement layout iterations for optimal performance.
• Specialize in advanced process node tapeouts, specifically leveraging TSMC 3nm process experience and design rules.
• Collaborate seamlessly with cross-functional design verification, physical design, and manufacturing operations squads.
• Ensure strict adherence to electromigration, IR drop, ESD protection, and DFM (Design for Manufacturing) standards.
• Maintain comprehensive layout documentation, DRC waiver logs, and tapeout checklist execution reports.

Required Qualifications & Skills:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics and Communication, VLSI Design, or related discipline.
• Minimum of 4+ years of progressive professional experience in analog and mixed-signal layout design within the semiconductor industry.
• Strong, demonstrable hands‑on professional expertise in custom layout tools (Cadence Virtuoso, Calibre, Hercules).
• Comprehensive working knowledge and practical proficiency in advanced node physical verification (DRC/LVS/PERC).
• Deep practical experience with TSMC advanced process nodes, specifically mandatory hands‑on TSMC 3nm process experience.
• Solid practical grasp of analog matching, noise reduction, shielding, and high‑frequency layout parasitics.
• Proven analytical, troubleshooting, and cross‑functional communication capabilities.
• Mandatory availability for a Face‑to‑Face (F2F) technical interview process in Hyderabad, India.

Nice-to-Have Skills:

• Professional training or certifications in advanced VLSI physical design and deep submicron layout methodologies.
• Prior professional working experience in top‑tier semiconductor product companies, foundries, or specialized IP design houses.
• Hands‑on familiarity with scripting languages like Python or SKILL for layout automation and productivity enhancement.
• Experience utilizing enterprise project management and ticketing platforms such as Jira and Confluence.
• Exposure to FinFET layout techniques, multi‑patterning constraints, and advanced packaging technologies.

Application Information:

• Recruiter: Logicsemi Technologies Recruitment Division
• Contact Name: Lakshmi L (HR Executive)
• Email: [e-mail]
• Phone:
• Company Website: https://www.logic-semi.com
• Salary/Rate: Market Competitive / Enterprise Semiconductor Package
• Deadline: Open until filled (Urgent Hyderabad Analog Layout Opening)
• Notice Period: Immediate to 30 Days Preferred
• Contract Duration: Permanent / Full-Time Engagement (Hyderabad)

Recruitment Pro Tip:

When applying for this Analog Layout Engineer position through Logicsemi Technologies, ensure your resume explicitly highlights your TSMC 3nm process layout portfolio, Cadence Virtuoso proficiency, and confirmation of your availability for an F2F interview in Hyderabad.