Design Verification (DV) – DDR Engineer | Logicsemi Technologies | Hyderabad

Logicsemi Technologies Pvt Ltd.; Hyderabad; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Logicsemi Technologies Pvt Ltd. in Hyderabad is seeking an experienced Design Verification (DV) – DDR Engineer on a permanent basis.

You will architect and implement UVM-based verification environments for DDR4/DDR5 memory controllers and PHY interfaces, ensuring protocol compliance and robust coverage. The role requires 4+ years in ASIC verification, strong SystemVerilog expertise, and willingness to participate in on-site interviews in Hyderabad.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics and Communication, VLSI Design, or related discipline.
• 4+ years of progressive professional experience in ASIC design verification and digital IC testing.
• Strong SystemVerilog and UVM expertise.
• Deep knowledge of high-speed memory protocols, especially DDR verification.
• Experience with constrained-random verification, functional coverage, and assertion-based verification (SVA).
• Hands-on debugging with simulators Cadence Xcelium, Synopsys VCS, and Mentor Questa.
• Excellent analytical and cross-functional communication skills.
• Willingness to attend Face-to-Face interviews in Hyderabad.

Responsibilities

• Architect, develop, and maintain SystemVerilog/UVM verification environments for DDR memory subsystems.
• Verify DDR4/DDR5/LPDDR controllers and PHY interfaces.
• Create reusable verification components, scoreboards, and coverage models.
• Run regression, debug simulations, and analyze waveform data to isolate issues.
• Maintain verification plans, bug logs, and regression records.
• Collaborate with ASIC design, RTL, and physical design teams.
• Participate in on-site F2F interviews and engineering reviews in Hyderabad.

Skills

SystemVerilog

UVM

DDR verification

Constrained-random

Functional coverage

SVA

Cadence Xcelium

Synopsys VCS

Mentor Questa

Cross-functional communication

Education

Bachelor’s or Master’s in Electrical Engineering / ECE / VLSI Design

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Position Summary

Driving advanced digital verification, memory subsystem validation, and high-speed DDR protocol verification in Hyderabad, Logicsemi Technologies is actively seeking an accomplished Design Verification (DV) – DDR Engineer for a permanent professional engagement. In this vital VLSI verification role, you will architect, develop, and execute robust verification environments for complex DDR memory controllers and physical interfaces, ensuring uncompromised protocol compliance, timing closure, and functional correctness. Bringing 4+ years of progressive professional experience in DDR design verification, you will empower global semiconductor leaders to achieve flawless silicon tapeouts. This prestigious career opportunity offers competitive remuneration, high technical visibility, and exceptional professional growth within a premier semiconductor solutions enterprise.

Detailed Job Description

As a Design Verification (DV) – DDR Engineer supporting Logicsemi Technologies in Hyderabad, India, you will take full operational, architectural, and tactical ownership of verification testbench development using SystemVerilog and UVM, assertion-based verification, and DDR protocol checking. Your day-to-day responsibilities include building constrained-random test environments, developing functional and code coverage closure plans, verifying DDR (DDR4/DDR5/LPDDR) controller and PHY interfaces, and participating in mandatory Face-to-Face (F2F) technical interviews in Hyderabad. You will collaborate closely with cross-functional design, architecture, and physical implementation squads. Furthermore, you will manage application requirements by submitting your updated resume via direct email to Lakshmi L at [e-mail].

Key Responsibilities

• Architect, develop, and maintain advanced SystemVerilog and UVM-based verification environments for complex DDR memory subsystems.


• Verify complex DDR (DDR4, DDR5, LPDDR4/LPDDR5) memory controllers, schedulers, and physical interface (PHY) layers.


• Write reusable verification components, interface agents, scoreboards, functional coverage models, and constrained-random stimulus generators.


• Execute regression test suites, debug simulation failures, analyze waveform traces, and isolate complex hardware bugs.


• Achieve rigorous functional and code coverage closure targets aligned with enterprise tapeout quality standards.


• Collaborate seamlessly with cross-functional ASIC design, RTL architecture, and physical design validation squads.


• Participate in mandatory Face-to-Face (F2F) technical interview evaluations and engineering reviews in Hyderabad.


• Maintain comprehensive verification plans, bug tracking logs, and regression audit documentation.

Required Qualifications & Skills

• Bachelor's or Master's degree in Electrical Engineering, Electronics and Communication, VLSI Design, or related discipline.


• Minimum of 4+ years of progressive professional experience in ASIC design verification and digital integrated circuit testing.


• Strong, demonstrable hands-on professional expertise in SystemVerilog and Universal Verification Methodology (UVM).


• Comprehensive working knowledge and practical proficiency in high-speed memory protocols, specifically DDR design verification.


• Deep practical experience in constrained-random verification, functional coverage analysis, and assertion-based verification (SVA).


• Solid practical grasp of simulation and debugging tools (Cadence Xcelium, Synopsys VCS, Mentor Questa).


• Proven analytical, troubleshooting, and cross-functional communication capabilities.


• Mandatory availability for a Face-to-Face (F2F) technical interview process in Hyderabad, India.

Nice-to-Have Skills

• Professional training or certifications in advanced VLSI verification methodologies and JEDEC memory standards.


• Prior professional working experience in top-tier semiconductor product companies, memory vendors, or IP design houses.


• Hands-on familiarity with scripting languages like Python or Perl for test automation and log parsing.


• Experience utilizing enterprise project management and ticketing platforms such as Jira and Confluence.


• Exposure to formal verification techniques and power-aware simulation (CPF/UPF).

Application Information

• Salary/Rate: Market Competitive / Enterprise Semiconductor Package


• Company Website: https://www.logic-semi.com


• Deadline: Open until filled (Urgent Hyderabad DDR DV Opening)


• Notice Period: Immediate to 30 Days Preferred


• Contract Duration: Permanent / Full-Time Engagement (Hyderabad)