Physical Design Director

Mulya Technologies; Hyderabad; Hybride; INR 3 200 000 - 5 600 000; Plein temps

Résumé du poste

Mulya Technologies in Hyderabad seeks a senior Physical Design Director to lead and grow the PD function. This role oversees end-to-end physical implementation of complex connectivity ASICs, drives PnR, CTS, routing, timing closure, and sign‑off for first-pass silicon in a fast-growing environment.

The ideal candidate will have deep hands-on full-chip PD expertise, a track record of multiple tapeouts at 7nm or below, and the leadership to scale a global PD team in collaboration with RTL, DV,

Qualifications

• Hands-on, full-chip physical design expertise for advanced nodes (7nm or below).
• Proven tapeout experience and leadership in PD teams.
• Strong scripting skills in TCL, Python, or Perl.

Responsabilités

• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII.
• Drive floor planning, placement, CTS, routing, timing closure, IR drop/EM, and physical verification (DRC/LVS).
• Lead timing closure across corners and modes; ensure robust STA sign-off at advanced nodes.
• Oversee power integrity and reliability analysis to meet design quality targets.
• Define PD team structure, hiring roadmap, and career development; mentor engineers.

Connaissances

Full-chip PD

Floorplanning

CTS/STA

IR/EM analysis

Scripting (Tcl/Python/Perl)

Team leadership

D2D/Interconnects

Formation

Bachelor's or Master’s in Electrical Eng / Electronics / CS

Outils

Cadence Innovus

Synopsys Fusion Compiler/IC Compiler

PrimeTime

Calibre

RedHawk/Voltus

Description du poste

Top30 Semiconductor Organization in the world

We provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, We enable organizations to unlock the full potential of modern AI. ’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.

Role Overvie w

We are seeking a Physical Design Director to lead and grow our Physical Design function in Hyderabad. This is a senior leadership role responsible for building and managing a high-performing PD team, driving physical implementation of complex, high-speed connectivity ASICs, and establishing best-in-class design methodology and flows.

The ideal candidate brings deep hands-on expertise in full-chip physical design at advanced nodes, a proven track record of successful tapeouts, and the leadership ability to scale a team and deliver results in a fast-paced, high-growth environment. This role will work closely with global PD, RTL, DV, DFT, and packaging teams to ensure first-pass silicon success.

Key Responsibilities

Leadership & Team Buiding

• Build, lead, and mentor a high-performing Physical Design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology fun ctionsDefine team structure, hiring roadmap, and career development paths for PD eng ineersFoster a culture of technical excellence, ownership, and continuous impro vementPartner with global PD leadership (US and Israel sites) to align on strategy, methodology, and execution priorities
• Physical Design Exe
• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII
• signoffDrive floor planning, placement, clock tree synthesis (CTS), routing, timing closure, power analysis (IR drop/EM), and physical verification (D RC/LVS)Lead timing closure across multiple corners and modes (MMMC), ensuring robust STA signoff at advanced nodes (5nm and
• below)Oversee power integrity and reliability analysis (IR drop, EM) to meet design quality and manufacturability
• targetsManage tapeout schedules,milestones, and cross-functional dependencies to deliver on time and within PPA targetsMethodology &a mp; CAD
• Establish and continuously improve PD flows, methodologies, checklists, and best practices for first-pass successEvaluate and deploy EDA tools (Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, RedHawk/Voltus, StarRC, etc.)Drive automation and scripting (Tcl, Python, Perl) to improve turnaround time and design qualityCollaborate with EDA vendors on tool evaluation, adoption, and methodology impr
• Cross-Functional Collaboration
• Partner closely with RTL, DV, DFT, packaging, and architecture teams to enable seamless integration of complex subsystems (SerDes, high-speed PHYs, die-to-die interfaces, etc.)Provide physical design input during architecture and floorplan feasibility studies, die sizing, and IP evaluationRepresent the Hyderabad PD team in global design reviews, tapeout readiness reviews, and leadership forums
• Basic Qualifications
• Bachelor's or master’s degree in electrical engineering, Electronics, or Computer Science18+ years of experience in ASIC physical design, with at least 5 years in a leadership or management roleShould be hands on with a proven track record of multiple successful tapeouts at advanced nodes (7nm or below); experience at 5nm/3nm strongly
• preferred
• Deep hands-on expertise in full-chip physical design: floorplanning, PnR, CTS, STA, IR/EM analysis, and physical verification
• Strong proficiency with industry-standard EDA tools: Cadence Innovus, Synopsys Fusion Compiler/IC Compiler, PrimeTime, Calibre, RedHawk/Voltus
• Experience with high-speed interface IPs such as SerDes, PCIe, CXL, or die-to-die (D2D/UCIe) interconnects
• Strong scripting skills in Tcl, Python, or Perl
• Demonstrated ability to build and lead global, cross-functional engineering teams
• Preferred Qualifications
• Experience with chiplet architecture, UCIe interfaces, or die-to-die physicalintegration
• Familiarity with low-power design techniques (UPF/CPF, multi-voltage domains)
• Experience working with TSMC advanced nodes and TSMC tapeout processes
• Background in networking, storage, or AI/ML
• Strong cross-functional collaboration skills with RTL, DFT, packaging, and silicon operations teams
• Experience establishing a PD center of excellence or greenfeld PDteam