Memory Circuit Design Verification Engineer

Weekday AI (YC W21); Hyderabad; Presencial; INR 900 000 - 1 300 000; Tempo integral

Resumo da oferta

Weekday AI (YC W21) in Hyderabad, India is seeking an experienced Memory Circuit Design Verification Engineer to verify and validate memory circuits, memory IP, and full-chip memory designs. You will develop verification strategies, run SPICE/FastSPICE simulations, and ensure timing compliance across PVT conditions.

The role collaborates with memory designers, circuit engineers, characterization specialists, and verification teams to identify design issues, improve methodologies, and deliver

Qualificações

• Hands-on experience in memory circuit design verification, memory IP validation, or related semiconductor verification activities.
• Strong understanding of SRAM and DRAM architectures, memory operation sequences, and fundamental memory timing concepts.
• Practical experience with SPICE and/or FastSPICE circuit simulations.
• Understanding of transistor-level and gate-level simulation methodologies.
• Proficiency in Verilog and/or SystemVerilog, including testbench development; UVM knowledge is beneficial where applicable.
• Strong knowledge of setup and hold timing, access time, critical paths, timing margins, and waveform analysis.
• Understanding of CMOS circuit fundamentals and transistor‑level schematics.
• Experience with PVT analysis, process corners, voltage and temperature variations, and design robustness validation.
• Strong debugging, failure analysis, and problem‑solving skills.
• Familiarity with scripting languages such as Python, Perl, Tcl, or Shell for test automation and verification‑flow development.
• Ability to collaborate effectively with circuit design, memory design, characterization, and verification teams.

Responsabilidades

• Memory Circuit Verification: Perform block-level and full-chip verification of memory circuits, memory IP, and associated design components.
• Verification Planning: Develop and execute verification plans, test cases, test vectors, testbenches, and simulation regressions to validate design functionality.
• Circuit Simulation: Run SPICE and FastSPICE simulations to verify circuit behavior, memory operations, and critical timing parameters.
• Gate-Level Verification: Execute gate-level simulations with timing delays and analyze logic schematics to identify functional and timing-related issues.
• Memory Timing Analysis: Evaluate read/write operations, setup and hold times, access time, critical data paths, timing margins, and other memory timing characteristics.
• Memory Architecture Validation: Verify memory architectures such as SRAM, DRAM, DDR, LPDDR, and emerging memory technologies based on project requirements.
• Debugging and Root‑Cause Analysis: Investigate functional failures, waveform mismatches, timing violations, and circuit‑level issues, collaborating with design teams to implement corrective actions.
• PVT and Corner Analysis: Validate design performance and reliability across process corners, voltage variations, temperature conditions, and speed grades.
• Verification Environment Development: Build, maintain, and enhance testbenches, verification environments, automation scripts, and regression frameworks.
• Regression and Coverage Analysis: Analyze simulation results, improve functional coverage, identify verification gaps, and optimize regression efficiency.
• Design Collaboration: Work with memory circuit designers and cross‑functional engineering teams to resolve design issues and improve overall design quality.
• Verification Sign‑Off: Support pre‑silicon verification sign‑off, maintain technical documentation, and communicate verification results and unresolved risks.

Conhecimentos

Memory verification

SRAM/DRAM architecture

SPICE/FastSPICE

Verilog/SystemVerilog

UVM knowledge

Timing analysis

PVT analysis

Python scripting

Cross-functional collaboration

Waveform analysis

Ferramentas

PrimeSim

FineSim

Spectre

HSPICE

Xcelium

SimVision

WaveView

Descrição da oferta de emprego

Job Description:

This role is for one of Weekday’s clients

Min Experience: 2+ years

Location: Hyderabad, Telangana, India

JobType: full-time

We are seeking an experienced Memory Circuit Design Verification Engineer to verify and validate complex memory circuits, memory IP, and full-chip memory designs. The ideal candidate will have a strong understanding of memory architectures, circuit-level simulation, digital verification, and timing analysis, with hands‑on experience in pre‑silicon verification and debugging.

In this role, you will develop and execute verification strategies, perform SPICE/FastSPICE and gate-level simulations, analyze critical memory timing parameters, and validate design robustness across process, voltage, and temperature (PVT) conditions. You will collaborate closely with memory designers, circuit engineers, characterization specialists, and design verification teams to identify design issues, improve verification methodologies, and ensure functional correctness and timing compliance.

Key Responsibilities

• Memory Circuit Verification: Perform block-level and full-chip verification of memory circuits, memory IP, and associated design components.
• Verification Planning: Develop and execute verification plans, test cases, test vectors, testbenches, and simulation regressions to validate design functionality.
• Circuit Simulation: Run SPICE and FastSPICE simulations to verify circuit behavior, memory operations, and critical timing parameters.
• Gate-Level Verification: Execute gate-level simulations with timing delays and analyze logic schematics to identify functional and timing-related issues.
• Memory Timing Analysis: Evaluate read/write operations, setup and hold times, access time, critical data paths, timing margins, and other memory timing characteristics.
• Memory Architecture Validation: Verify memory architectures such as SRAM, DRAM, DDR, LPDDR, and emerging memory technologies based on project requirements.
• Debugging and Root‑Cause Analysis: Investigate functional failures, waveform mismatches, timing violations, and circuit‑level issues, collaborating with design teams to implement corrective actions.
• PVT and Corner Analysis: Validate design performance and reliability across process corners, voltage variations, temperature conditions, and speed grades.
• Verification Environment Development: Build, maintain, and enhance testbenches, verification environments, automation scripts, and regression frameworks.
• Regression and Coverage Analysis: Analyze simulation results, improve functional coverage, identify verification gaps, and optimize regression efficiency.
• Design Collaboration: Work with memory circuit designers and cross‑functional engineering teams to resolve design issues and improve overall design quality.
• Verification Sign‑Off: Support pre‑silicon verification sign‑off, maintain technical documentation, and communicate verification results and unresolved risks.

Required Skills and Qualifications

• Hands‑on experience in memory circuit design verification, memory IP validation, or related semiconductor verification activities.
• Strong understanding of SRAM and DRAM architectures, memory operation sequences, and fundamental memory timing concepts.
• Practical experience with SPICE and/or FastSPICE circuit simulations.
• Understanding of transistor‑level and gate‑level simulation methodologies.
• Proficiency in Verilog and/or SystemVerilog, including testbench development; UVM knowledge is beneficial where applicable.
• Strong knowledge of setup and hold timing, access time, critical paths, timing margins, and waveform analysis.
• Understanding of CMOS circuit fundamentals and transistor‑level schematics.
• Experience with PVT analysis, process corners, voltage and temperature variations, and design robustness validation.
• Strong debugging, failure analysis, and problem‑solving skills.
• Familiarity with scripting languages such as Python, Perl, Tcl, or Shell for test automation and verification‑flow development.
• Ability to collaborate effectively with circuit design, memory design, characterization, and verification teams.

Good‑to‑Have Skills

• Experience with custom memory IP verification or full‑chip memory circuit validation.
• Knowledge of DDR, LPDDR, and other advanced memory architectures.
• Understanding of analog/mixed‑signal circuit behavior and CMOS/FinFET technologies.
• Experience with full‑chip analog SPICE simulation and timing sign‑off.
• Familiarity with memory compiler verification, memory characterization, and Liberty (.lib) model validation.
• Exposure to industry‑standard EDA tools such as PrimeSim, FineSim, Spectre, HSPICE, Xcelium, SimVision, or WaveView.
• Experience developing automation frameworks and improving verification workflows.
• Strong documentation, communication, analytical, and cross‑functional collaboration skills.