Design Engineer II – Memory Layout

SIGNOFF SEMICONDUCTORS PVT. LTD.; Bengaluru; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

SIGNOFF SEMICONDUCTORS PVT. LTD. in Bengaluru seeks a Memory Layout Engineer to design and optimize memory macros (SRAM/MRAM). You will work with circuit teams, perform physical verification, and drive layout quality across projects.

Candidates should have 3–5 years in memory layout, strong CMOS fundamentals, and proficiency with Cadence Virtuoso and Calibre. The role is on-site with global collaboration across time zones.

Qualifications

• BE/B.Tech in ECE/EEE or M.Tech in VLSI as stated.
• 3–5 years of experience in memory/layout design.
• Strong fundamentals in CMOS devices and RC networks.

Responsibilities

• Design and develop custom layouts for memory macros (SRAM, MRAM).
• Create and optimize layouts for memory sub-blocks (row decoders, sense amps, drivers).
• Collaborate with circuit designers to meet performance and area targets.
• Perform DRC/LVS/ERC checks and address reliability issues.
• Mitigate layout-dependent effects and parasitics affecting performance.
• Drive layout quality and best practices across projects.
• Support distributed teams and client engagements.

Skills

CMOS concepts

Custom memory layout

EDA tools

Layout optimization

Design collaboration

Debugging & analysis

Communication skills

Education

BE/B.Tech in ECE/EEE or M.Tech in VLSI

Tools

Cadence Virtuoso

Synopsys Custom Compiler

Calibre

ICV

Job description

SIGNOFF SEMICONDUCTORS PVT. LTD. | Full time

SignOff Semiconductors is a consulting company that was founded in 2015 by a group of semiconductor professionals. Since then, the company has provided design services to several companies in the semiconductor industry through continuous service partnerships. SignOff semiconductors is a fast-growing company with a deep focus on getting excellent talent from the industry as well as picking exceptional talent from the academics.

Our unique and transparent work culture has helped us to retain the best talent and we collectively deliver high quality design services. Our team has a vast experience, and we can serve our clients on various services like Physical Design, Full Custom Analog and Digital Custom Layout and Verification, RTL Design, Verification, Embedded and Firmware.

SignOff Semiconductor has offices in Bengaluru, Hyderabad, Toronto (Ontario, Canada), and California (US) in order to serve its customer based on their asks & needs.

Job Description

We are seeking a highly motivated Memory Layout Engineer with strong expertise in custom layout development for advanced memory compilers. The ideal candidate will have hands-on experience in SRAM/MRAM layout design, physical verification, and close collaboration with circuit design teams to deliver high-quality layouts for advanced technology nodes.

Key Responsibilities

• Design and develop custom layouts for memory macros, including SRAM, MRAM, and other embedded memory architectures.
• Create and optimize hierarchical layouts for memory sub-blocks such as row decoders, write drivers, sense amplifiers, assist circuits, and memory control logic.
• Collaborate closely with circuit designers to ensure layout implementation meets performance, area, power, reliability, and manufacturability requirements.
• Perform and resolve physical verification checks including DRC, LVS, ERC, and reliability-related violations.
• Analyze and mitigate layout-dependent effects, parasitics, and other second-order effects impacting circuit performance.
• Drive layout quality, productivity improvements, and best practices across memory design projects.
• Support project execution across distributed teams and customer engagements.

Required Skills & Experience

• Strong understanding of VLSI fundamentals, including CMOS devices, IC fabrication processes, FinFET technology, and RC network concepts.
• Hands-on experience in custom memory layout development for SRAM, MRAM, or similar memory architectures.
• Proficiency with industry-standard EDA tools such as Cadence Virtuoso, Synopsys Custom Compiler, Calibre, ICV, or equivalent.
• Good understanding of layout optimization techniques involving speed, area, power, parasitics, matching, electromigration, and reliability considerations.
• Experience working closely with design teams to achieve design specifications and signoff requirements.
• Strong debugging, problem-solving, and analytical skills.
• Excellent verbal and written communication skills.

Preferred Qualifications

• Experience with advanced process technologies and high-density memory designs.
• Ability to independently drive complex layout tasks from concept to tape-out.
• Experience mentoring junior engineers and leading small technical teams.
• Strong documentation, presentation, and stakeholder management skills.

Requirements

Education
BE/B.Tech in ECE/EEE or M.TechVLSI

Experience
3 - 5 Years

• Flexibility to work from client locations and Offshore Development Centers (ODC) as required.
• Comfortable working with global cross-functional teams across multiple time zones.
• Self-driven professional capable of taking ownership and delivering results in a fast-paced environment.