Physical Design Lead (8+ Years)

ACL Digital; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

ACL Digital is seeking a Physical Design Lead to drive block/top-level execution on 7nm / 5nm / 3nm nodes. The role requires strong hands-on Innovus (P&R) and Tempus (STA) experience, plus leadership to manage full ASIC PD flow including floorplanning, power grid, CTS, and timing closure to sign-off (GDSII).

You will also oversee MMMC STA, SI/crosstalk analysis, ECO generation, and ensure zero design rule violations using Calibre or Pegasus, with scripting in TCL/Perl/Python to automate flows.

Qualifications

• Lead full ASIC PD flow: Floorplanning, Power Grid, CTS, Timing Closure, and Sign-off (GDSII).
• Drive MMMC STA, SI/crosstalk analysis, and ECO generation.
• Ensure zero DRC/LVS/DFM errors using Calibre / Pegasus.
• Strong TCL/Perl/Python scripting for flow automation.
• B.Tech / M.Tech in ECE, EEE, or VLSI.

Responsibilities

• Lead full ASIC PD flow: Floorplanning, Power Grid, CTS, Timing Closure, and Sign-off (GDSII).
• Drive MMMC STA, SI/crosstalk analysis, and ECO generation.
• Ensure zero DRC/LVS/DFM errors using Calibre / Pegasus.
• Strong TCL/Perl/Python scripting for flow automation.

Skills

ASIC Physical Design

Leadership

Floorplanning

Timing Closure

Education

B.Tech/M.Tech in ECE/EEE or VLSI

Tools

Innovus (P&R)

Tempus (STA)

Calibre

Pegasus

TCL scripting

Perl scripting

Python scripting

Job description

ACL Digital is hiring a Physical Design Lead for block/top-level execution on 7nm / 5nm / 3nm nodes.

Mandatory Requirement:Cadence Toolchain Expertise: Strong hands-on experience in Innovus (Pamp;R) amp; Tempus (STA) is mandatory.Key Responsibilities amp; Requirements:Lead full ASIC PD flow: Floorplanning, Power Grid, CTS, Timing Closure, and Sign-off (GDSII).Drive MMMC STA, SI/crosstalk analysis, and ECO generation.Ensure zero DRC/LVS/DFM errors using Calibre / Pegasus.Strong TCL/Perl/Python scripting for flow automation.B.Tech / M.Tech in ECE, EEE, or VLSI.