\"Lead Physical Design Engineer\"

SiMaxTech Pvt Ltd; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

SiMaxTech Pvt Ltd in Bengaluru is seeking a Lead Physical Design Engineer with deep Cadence Innovus expertise to drive RTL-to-GDSII flow for complex SoCs and mentor teams.

The ideal candidate will lead floorplanning, placement, routing, timing closure, and physical verification, collaborate with RTL/DFT/packaging groups, and develop automation scripts to improve tape-out quality.

Qualifications

• 7-9 years of experience in physical design or RTL-to-GDSII flows.
• Strong hands-on Cadence Innovus expertise in complex SoCs.
• Experience with timing closure, physical verification, and mentoring teams.

Responsibilities

• Lead end-to-end Physical Design from Netlist to GDSII.
• Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Optimization using Cadence Innovus.
• Drive timing closure across all PVT corners using Tempus/PrimeTime.
• Conduct congestion analysis and optimize Power, Performance, and Area (PPA).
• Resolve setup/hold violations and execute ECO implementation.
• Perform Physical Verification including DRC, LVS, Antenna, and Density checks.
• Work on IR Drop and EM analysis using Voltus/RedHawk.
• Collaborate with RTL, DFT, STA, Verification, and Packaging teams for tape-outs.
• Develop automation scripts using Tcl, Perl, Python, or Shell.
• Mentor junior engineers and review design quality.
• Support multiple project tape-outs while ensuring schedule adherence.

Skills

Cadence Innovus

Timing closure

Physical Verification

Mentoring

Automation scripting

Tools

Tempus

PrimeTime

Voltus

RedHawk

Job description

Job Title: Lead Physical Design Engineer

Experience: 7-9 Years

Employment Type: Full-Time

Job Summary

SiMaxTech is looking for an experienced Lead Physical Design Engineer with strong expertise in Cadence Innovus to drive the complete RTL-to-GDSII implementation flow for complex SoCs. The ideal candidate should have hands-on experience in advanced technology nodes, timing closure, physical verification, and mentoring engineering teams while ensuring high-quality tape-outs.

Key Responsibilities

• Lead end-to-end Physical Design implementation from Netlist to GDSII.
• Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Optimization using Cadence Innovus.
• Drive timing closure across all PVT corners using Tempus/PrimeTime.
• Perform congestion analysis and optimize Power, Performance, and Area (PPA).
• Resolve setup/hold violations and execute ECO implementation.
• Perform Physical Verification including DRC, LVS, Antenna, and Density checks.
• Work on IR Drop and EM analysis using Voltus/RedHawk.
• Collaborate with RTL, DFT, STA, Verification, and Packaging teams for successful tape-outs.
• Develop automation scripts using Tcl, Perl, Python, or Shell.
• Mentor junior engineers and review design quality.
• Support multiple project tape-outs while ensuring schedule adherence and design quality