Senior Physical Design Engineer

ACL Digital; Bengaluru; On-site; INR 1,400,000 - 2,300,000; Full time

Job summary

ACL Digital in Bengaluru is seeking a Senior Physical Design Engineer with 5+ years of hands-on experience to drive RTL-to-GDSII flow on advanced nodes, including floorplanning, placement, CTS, routing and timing closure. You will collaborate with Front‑End, DFT and package teams to tape-out critical designs.

Expertise in STA, DRC/LVS/ERC, low-power techniques (UPF/CPF, Clock Gating, Multi-VT) and scripting in Tcl/Perl/Python, plus proficiency with Innovus, ICC2, Primetime, Calibre and

Qualifications

• 5+ years hands-on experience in physical design flows.
• Immediate to 30 days notice period.

Responsibilities

• Lead Netlist-to-GDSII flow including Floorplanning, Placement, CTS, Routing, and Timing Closure (STA).
• Execute STA, cross-talk analysis, IR-drop/EM, and DRC/LVS/ERC checks.
• Hands-on work on lower-node designs (7nm/5nm/3nm).
• Collaborate with Front-End, DFT and Package teams for tape-out.
• Utilize industry tools: Innovus, ICC2, Primetime, Calibre, Voltus/StarRC.
• Apply low-power techniques (UPF/CPF, Clock Gating, Multi-VT) and scripting (Tcl/Perl/Python).

Tools

Innovus

ICC2

Primetime

Calibre

Voltus/StarRC

Job description

WE ARE HIRING: Senior Physical Design Engineer

ACL Digital is expanding its Semiconductor/VLSI practice in Bengaluru! We are looking for an experienced Physical Design Engineer with 5+ years of hands‑on expertise to drive full-flow RTL-to-GDSII execution on advanced technology nodes.

• Role: Physical Design Engineer
• Experience Required: 5+ Years
• Notice Period: Immediate to 30 Days ONLY

Key Responsibilities:

• Lead Netlist-to-GDSII flow including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Timing Closure (STA).
• Execute Static Timing Analysis (STA), cross-talk noise analysis, power network analysis (IR-drop/EM), and Physical Verification (DRC/LVS/ERC).
• Hands‑on work on lower-node designs (e.g., 7nm / 5nm / 3nm).
• Collaborate with Front-End, DFT, and Package design teams for successful tape‑out execution.
• Proven expertise in standard industry EDA tools (Innovus, ICC2, Primetime, Calibre, Voltus/StarRC).
• Strong understanding of low‑power design methodologies (UPF/CPF, Clock Gating, Multi-VT).
• Excellent scripting skills in Tcl, Perl, or Python for flow automation.