Lead Physical Design Engineer

ACL Digital; Chennai District; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

A leading tech firm in Chennai seeks an experienced Lead Physical Design Engineer with expertise in ASIC physical design. Candidates should have strong hands-on experience with Cadence Innovus and a deep understanding of the end-to-end design flow. Responsibilities include floorplanning, placement, and driving timing closure. The ideal candidate will possess 8+ years of experience and knowledge of advanced technology nodes. This role offers a competitive salary and opportunities for professional growth.

Qualifications

• 8+ years of experience in Physical Design Engineering.
• Strong hands-on expertise in end-to-end ASIC physical design flow.
• Experience with advanced technology nodes (7nm, 5nm is a plus).

Responsibilities

• Manage floorplanning, placement, and routing.
• Perform physical verification and drive timing closure.
• Collaborate with RTL, DFT, STA, and verification teams.

Skills

Physical Design flow expertise

Hands-on with Cadence Innovus

Timing analysis tools (Synopsys PrimeTime)

Signal integrity and noise analysis

Low power techniques

Scripting (TCL, Shell, Python)

Tools

Cadence Innovus

Synopsys PrimeTime

Job description

Job Title: Lead Physical Design Engineer

Company: ACL Digital

Experience: 8+ Years

Job Summary

We are looking for an experienced Physical Design Engineer with strong hands‑on expertise in end‑to‑end ASIC physical design flow. The ideal candidate should have deep knowledge of implementation using Cadence Innovus and be capable of handling complex SoC blocks independently.

Key Responsibilities

• Floorplanning
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Physical Verification
• Work extensively with Cadence Innovus for implementation and optimization
• Drive timing closure, congestion analysis, and power optimization
• Handle IR drop, EM analysis, and physical signoff checks
• Collaborate with RTL, DFT, STA, and verification teams
• Debug and resolve DRC/LVS issues and ensure clean tapeout
• Work on advanced technology nodes (e.g., 7nm, 5nm is a plus)

Required Skills

• Strong expertise in Physical Design flow from Netlist to GDSII
• Hands‑on experience with:
• Cadence Innovus
• Timing analysis tools like Synopsys PrimeTime
• Solid understanding of:
• Timing closure (setup/hold fixing)
• Signal integrity and noise analysis
• Low power techniques
• Experience with scripting (TCL, Shell, Python is a plus)
• Good debugging and problem‑solving skills