Senior Physical Design Engineer

BITSILICA; Hyderabad; Sur place; INR 1 000 000 - 1 500 000; Plein temps

Résumé du poste

A semiconductor design company in Hyderabad is seeking a Physical Design Engineer with over 4 years of experience to handle block-level implementation tasks from RTL to GDSII. The ideal candidate will have familiarity with advanced nodes (3nm to 7nm), perform sign-off analysis, and optimize designs for performance, power, and area. Proficiency in EDA tools and scripting with Tcl and Perl/Python is essential. This role offers an opportunity to work on cutting-edge technology in a dynamic environment.

Qualifications

• 4+ years of experience in Physical Design Implementation.
• Proven track record with advanced nodes of 3nm/4nm/5nm/7nm.
• Experience with sign-off analysis including STA and formal verification.

Responsabilités

• Perform block level physical implementation tasks from RTL to GDSII.
• Optimize designs for Performance, Power, and Area (PPA).
• Conduct static timing analysis and physical verification for tapeout.

Connaissances

Physical Design Implementation

Scripting with Tcl

Scripting with Perl/Python

Outils

DC/Genus

ICC2

Innovus

Calibre

Description du poste

• 4+ years of experience in Physical Design Implementation
• Perform block level physical implementation tasks from RTL to GDSII including synthesis, floorplanning, power planning, placement, Clock Tree Synthesis (CTS) and routing.
• Proven track record with advanced nodes of 3nm/4nm/5nm/7nm with successful tapeouts
• Perform sign-off analysis and closure on Static Timing Analysis (STA), formal verification (LEC), power analysis (EMIR), and physical verification (DRC/LVS/ERC) for tapeout.
• Optimize designs for Performance, Power, and Area (PPA) by improving congestion, timing, and power consumption.
• Experience with EDA tools in DC/Genus, ICC2/FC/Innovus, PT/Tempus, Calibre/ICV/Pegasus.
• Proficient in scripting with Tcl and Perl/Python