Physical Design Engineer

Mirafra Technologies; Bengaluru; On-site; INR 1,000,000 - 1,400,000; Full time

Job summary

Mirafra Technologies is seeking an experienced ASIC Physical Design Engineer in Bengaluru, India. The role involves floorplanning, power planning, placement, and ensuring timing and power integrity closure. The ideal candidate will have 3–5 years of experience with tools like Cadence Innovus or Synopsys ICC/ICC2, and a deep understanding of Netlist to GDSII flow. A B.E/B.Tech or M.E/M.Tech in Electronics or Electrical is required. This position offers opportunities for significant collaboration across teams.

Qualifications

• 3–5 years experience in ASIC physical design.
• Strong expertise in Cadence Innovus or Synopsys ICC/ICC2.
• Deep understanding of Netlist to GDSII flow.

Responsibilities

• Perform floorplanning, power planning, placement, CTS, and routing.
• Ensure timing, power integrity, and physical verification closure.
• Coordinate with RTL design, STA, and verification teams.

Skills

ASIC physical design experience

Cadence Innovus

Synopsys ICC/ICC2

Netlist to GDSII flow understanding

Education

B.E/B.Tech or M.E/M.Tech in Electronics/Electrical

Job description

Physical Implementation: Perform floorplanning, power planning, placement, Clock Tree Synthesis (CTS), and routing for complex, timing‑critical blocks or full‑chip top‑level integration.

Signoff Closure: Ensure timing (STA), power integrity, and physical verification (DRC/LVS/ERC/ESD) closure on advanced technology nodes (5nm, 4nm, 3nm).

Collaboration: Coordinate with RTL design, STA, and verification teams.

Requirements & Qualifications

• Experience: 3–5 years on ASIC physical design.
• Tools: Strong expertise in Cadence Innovus or Synopsys ICC/ICC2.
• Technical Knowledge: Deep understanding of Netlist to GDSII flow
• Education: B.E/B.Tech or M.E/M.Tech in Electronics/Electrical