Memory Design Engineer

Broadcom; Bengaluru; On-site; INR 1,400,000 - 2,400,000; Full time

Job summary

Broadcom Bengaluru is seeking a Memory Design Engineer to contribute to design and development of SRAMs and memory compilers across 28nm/16FF/7FF/5FF tech nodes. Responsibilities include circuit design, timing, margin analysis, SI/PI, and silicon debugging.

Experts with high-speed CMOS design, memory compilers, and Cadence/Mentor flows are preferred, with 2+ years for Masters or 3+ years for Bachelors. Equal opportunity employer.

Qualifications

• Expertise in high speed, low power CMOS circuit design and timing.
• Experience driving memory compiler specifications to release.
• Knowledge of split-rail, power gating architectures.
• Hands-on silicon debugging and failure analysis.
• 5+ years of Cadence/Mentor schematic/layout tool experience.

Responsibilities

• Design and development of SRAMs and register files for multiple technologies.
• Circuit design/simulation of bitcells, decoders, and control logic.
• Develop margins and characterization flows for sign-off.
• Perform SI and power integrity analyses for memory designs.
• Conduct timing analysis of critical paths in high-speed memory.
• Perform stress analysis and yield sign-off activities.
• Collaborate with cross-functional teams to meet performance targets.

Skills

High speed/low power CMOS design

Clocking scheme

Static and dynamic logic circuits

Memory compiler design

Cadence/Mentor tools

Circuit simulation (HSPICE/HSIM)

Scripting: Perl/Python

Sub-nanometer layout issues

Memory DFT understanding

Education

Masters degree with 2+ years

Bachelor's degree with 3+ years

Tools

Cadence

Mentor

HSPICE

HSIM

XA

FinSim

XARA

nWave

Job description

Job Description:

JD for Memory Design Engineer

1. Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies
2. Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
3. Development of critical path and characterization flow to perform detailed margin and characterization simulations.
4. Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
5. Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
6. Logic simulations and detailed timing analysis of key paths in high speed memory design.
7. Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.

Skill Sets/Prerequisites

1. Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
2. Experience in Designing and driving one or many Memory Compilers Specifications to final release
3. Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
4. Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.
   5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools
5. Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
6. Experience in Skill/Perl/Python Scripting is a strong plus
7. Experience in Understanding the layout design issues in sub nanometer regime is a must.

1. Expertise in Understanding Memory DFT is a Plus.
2. Masters Degree with 2+ Years or Bachelors Degree with 3+ years

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.