Associate II - VLSI

UST; Hyderabad; On-site; INR 850,000 - 1,150,000; Full time

Job summary

UST is seeking an Engineering - Hardware Design Engineer 2 in Hyderabad, India. The role focuses on memory technologies, memory compilers, and VLSI synthesis workflows.

You will support multiple globally distributed projects, read documentation, answer end-user questions, and generate and QA memory views for each release version. Ideal candidates have 2–4 years of experience, strong knowledge of SRAMs, Verilog, SPICE, and scripting in PERL/Python, with hands-on physical design verification

Qualifications

• Understanding of SRAMs and memory compilers; Synopsys memory compiler experience preferred.
• Familiarity with memory design and views (Verilog, timing .lib, LEF, GDS).
• Familiarity with physical design verification (DRC and LVS).
• Ability to run and interpret SPICE simulations.
• Ability to write/modify scripts in PERL, Unix shell, Tcl, Python.

Responsibilities

• Read and understand documentation, answer end-user questions regarding memory compilers.
• Generate compiled memory views and QA views for each release version.
• Perform program management: track actions and progress against due dates.
• Support multiple projects in a globally distributed team.

Skills

Design Verification

Hardware Design

Physical Design

Program Management

Python

Testing

VLSI

Tools

Calibre

Synopsys Memory Compiler

Job description

Role Description

Job Title: Engineering - Hardware Design Engineer 2 Job Description: JOB DUTIES: Must solid experience with memory technologies, and a desire to develop broader exposure to their downstream use in a dynamic, cutting edge VLSI Synthesis environment. This role will provide key support for multiple projects in a globally distributed team. Responsibilities will include: Read and understand documentation of and answer end-user question regarding Synopsys memory compilers Generate compiled memory views and perform quality assurance on those views for each released version. Perform program management, tracking action items and progress against due dates. EXPERIENCE AND EDUCATION: Understanding of SRAMs and memory compilers (Synopsis Memory Compiler experience preferred) as well as VLSI design flow;Familiarity with memory design and views of memories, e.g. Verilog, timing (.lib), LEF, GDS;Familiarity with physical design verification, e.g. DRC and LVS;Able to perform and interpret circuit simulations, e.g. using SPICE;Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language. 2-4 years of experience Release Comments: Skills:4 to 6 year's experiencePhysical Design floor planning including power grid designunderstanding of timing concepts and signoffGood hands-on experience in analyzing and fixing physical DRCs and analyzing LVS issues in Calibre tool

Skills

• Design Verification
• Hardware Design
• Physical Design
• Program Management
• Python
• Testing
• VLSI