Physical Design Engineer

PerfectVIPs; Pune District; On-site; INR 900,000 - 1,400,000; Full time

Job summary

PerfectVIPs is seeking a seasoned Physical Design engineer to own block-level implementation. The role covers end-to-end physical design activities from synthesis to tape-out on advanced nodes (16nm and below).

You will drive timing closure, power integrity analysis, and layout verification, coordinating with design teams to ensure convergence and high-quality tape-out readiness. The ideal candidate has hands-on experience across floor planning, placement, CTS, routing, DFM checks, and parasitic

Qualifications

• Participated in all stages of design: floor planning, placement, CTS, routing, crosstalk avoidance, physical verification.
• Well-versed with Level timing closure (STA) and timing closure methodologies.
• Experience estimating power using industry standard tools, designing power grid, analyzing power grid, static IR drop, dynamic IR drop.
• Analyze DRC, LVS, ERC rule files for layout verification.

Responsibilities

• Take complete ownership for implementation of Block level designs.
• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below.
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM).
• Well aware of place and route methodologies and hands on experience with timing convergence.

Skills

Timing closure

Power integrity

Place & Route

Floor planning

Synthesis

Tools

IR drop analysis tools

DFM tools

Timing analysis tools

Layout verification tools

Job description

• Take complete ownership for implementation of Block level designs
• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
• Well versed with the Level timing closure (STA), Timing closure methodologies
• Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
• Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
• Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
• Well aware of place and route methodologies and hands on experience with timing convergence
• Good communication skill to negotiate with top level for convergence