Physical Design Engineer

PerfectVIPs; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

PerfectVIPs is seeking an experienced Physical Design Engineer to own block-level design and drive the complete flow from synthesis to tape-out on sub-16nm nodes. The role emphasizes robust timing closure, power integrity analysis, and tight collaboration with top-level teams to ensure convergence across CTS, routing, and verification.

The candidate will work through 16nm and smaller nodes, applying power grid analysis, DFM checks, and thorough verification.

Responsibilities

• Own block-level physical design implementation and validation.
• Plan and execute all physical design aspects: synthesis, floor planning, place & route, CTS, timing closure, and tape-out on 16nm nodes or below.
• Participate in all design stages: floor planning, placement, CTS, routing, and verification.
• Master Level timing closure (STA) and timing convergence.
• Estimate and analyze power grid, perform static and dynamic IR drop analysis.
• Review DRC, LVS, ERC rule files for layout verification.
• Work with 16/14/10/7nm nodes and push for timing convergence.
• Communicate effectively with top-level to achieve convergence.

Job description

• Take complete ownership for implementation of Block level designs
• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
• Well versed with the Level timing closure (STA), Timing closure methodologies
• Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
• Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
• Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
• Well aware of place and route methodologies and hands on experience with timing convergence
• Good communication skill to negotiate with top level for convergence