Physical Design Engineer/Lead - Noida

eInfochips (An Arrow Company); Dadri; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

A leading semiconductor firm in India seeks an experienced Physical Design Engineer with 8 to 15 years of expertise. The role involves handling the physical design process from netlist to GDSII, integrating blocks including analog IP, and performing physical verification signoff. Candidates should have experience with GHz clock frequency chips and a strong foundation in automation languages such as shell, Tcl, Perl, or Python. Familiarity with tooling like ICC2, Innovus, and Calibre is essential for success in this position.

Qualifications

• 8 to 15 years of hands-on experience in Physical Design.
• Experience in top-level floorplanning, block partitioning, and power planning.
• Designed complex chips in technology nodes of 16nm and below.

Responsibilities

• Plan and execute physical design from netlist to GDSII.
• Integrate blocks including analog IP and perform physical verification signoff.
• Handle chips with GHz clock frequencies.

Skills

Physical Design

Floorplanning

Power Planning

Clock Mesh Structure

Physical Verification

Automation (shell/tcl/perl/python)

Tools

ICC2

Innovus

Calibre

Formality

LEC

Job description

• 8 to 15 Years of Hands on Experience in Physical Design (Netlist to GDSII)
• Proven experience in top level floorplanning/block partitioning, power planning
• Understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
• Engineer should have experience in handling chips of GHz clock frequency range & multi-million instance.
• Should have designed complex chips in lower technology nodes (16nm and below).
• Padframe/BGA planning/design, including RDL routing is required.
• In Depth experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.
• Good exposure in Floorplanning, CTS, STA, Physical Verification, Basic understanding of timing constraints.
• Good exposure to ICC2/Innovus/Calibre/Formality/LEC tool set.
• Well versed in automation skills using shell/tcl/perl/python