Physical Design Engineer

PerfectVIPs; Dadri; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

PerfectVIPs in India is seeking a seasoned Physical Design Engineer to own block-level implementation across 16nm and below nodes. You will drive Synthesis, Floorplanning, Place-and-Route, CTS, clock distribution, and IP integration, ensuring power and timing closure.

You will analyze DRC/LVS/ERC, perform IR drop checks, and contribute to tape-out readiness. Strong communication is required to coordinate with topology and foundry teams.

Qualifications

• Experience implementing block-level designs in complex PD flows.
• Hands-on with floor planning, synthesis, CTS, P&R, and timing closure.
• Experience with DRC, LVS and ERC verification procedures.
• Power analysis and IR drop analysis in standard PD environments.
• Power grid design and IP integration knowledge.
• Excellent communication skills for convergence discussions with senior teams.

Responsibilities

• Take complete ownership for implementation of Block level designs.
• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
• Well versed with the Level timing closure (STA), Timing closure methodologies
• Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
• Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
• Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
• Well aware of place and route methodologies and hands on experience with timing convergence
• Good communication skill to negotiate with top level for convergence

Skills

Block-level design ownership

Physical Design planning

Synthesis

Floor planning

Place and Route

Timing closure

Power/IR drop analysis

DRC/LVS/ERC analysis

Communication skills

Tools

Industry standard PD tools

Job description

• Take complete ownership for implementation of Block level designs
• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
• Well versed with the Level timing closure (STA), Timing closure methodologies
• Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
• Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
• Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
• Well aware of place and route methodologies and hands on experience with timing convergence
• Good communication skill to negotiate with top level for convergence