Physical Design Engineer

PerfectVIPs; Khordha; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

PerfectVIPs is seeking an experienced physical design engineer to take ownership of block-level design and drive the PHY flow from synthesis to tape-out on leading nodes. The role requires hands-on experience with floor planning, place & route, CTS, and timing convergence.

You will collaborate with top-level teams to ensure robust power integrity and adherence to DFM and sign-off checks. The ideal candidate has strong STA knowledge, proven convergence skills, and excellent communication to

Qualifications

• Experience in complete physical design flow from floor planning to tape-out.
• Strong knowledge of STA and timing closure methodologies.
• Experience with power integrity analysis and IR drop checks.
• Familiar with DRC, LVS, ERC rule files.
• Experience on 16nm/14nm/10nm/7nm nodes.
• Excellent communication to negotiate convergence.

Responsibilities

• Take ownership for implementation of block level designs.
• Plan and execute physical design including synthesis, floor planning, placement and routing.
• Participate in CTS, timing convergence, and topology verification.
• Analyze power grid and perform static and dynamic IR drop analysis.
• Review DRC, LVS, ERC rule files for layout verification.
• Work on leading nodes 16nm, 14nm, 10nm, 7nm.
• Coordinate with top level for convergence.

Skills

Block-level design

Synthesis

Floor planning

Place & Route

Clock tree synthesis

Clock distribution

IP integration

Extraction

Timing closure

Power integrity

Physical verification

DFM

Job description

• Take complete ownership for implementation of Block level designs
• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
• Well versed with the Level timing closure (STA), Timing closure methodologies
• Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
• Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
• Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
• Well aware of place and route methodologies and hands on experience with timing convergence
• Good communication skill to negotiate with top level for convergence