Physical Design Engineer

Allegis Group; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Allegis Group in Bengaluru seeks highly skilled Physical Design Engineers with hands-on, end-to-end PD experience across RTL to GDSII, emphasis on timing closure, PnR, and sign-off methodologies in a fast-paced semiconductor design environment.

You will collaborate across RTL, DFT, architecture and signoff teams to resolve congestion, timing, noise and power issues while delivering PD results that meet aggressive performance, power and area targets using industry-standard tools.

Qualifications

• Hands-on experience executing full-chip Physical Design from RTL to GDSII.

Responsibilities

• Execute full-chip and block-level Physical Design flows, from RTL to GDSII.
• Perform Place & Route (PnR) using industry-standard tools.
• Conduct Static Timing Analysis (STA), debug timing issues, and drive complete timing closure.
• Support synthesis, floor planning, clock tree synthesis (CTS), routing, and physical verification.
• Collaborate closely with RTL, DFT, architecture, and signoff teams for seamless integration.
• Analyse and resolve congestion, timing, noise, and power-related challenges.
• Ensure delivery of highquality results that meet performance, power, and area (PPA) targets.

Skills

PnR (Place & Route)

STA hands-on

EDA tools (Synopsys, Cadence)

Tools

Synopsys tools

Cadence tools

Job description

Role Overview:

We are seeking highly skilled Physical Design Engineers with strong expertise in advanced implementation flows. The ideal candidates will have hands-on, end-to-end physical design experience, with a solid understanding of timing closure, PnR, and sign-off methodologies. This role requires strong analytical skills, problemsolving capabilities, and the ability to work in a fast-paced semiconductor design environment.

Key Responsibilities:

• Execute fullchip and blocklevel Physical Design flows, from RTL to GDSII.
• Perform Place & Route (PnR) using industry-standard tools.
• Conduct Static Timing Analysis (STA), debug timing issues, and drive complete timing closure.
• Support synthesis, floor planning, clock tree synthesis (CTS), routing, and physical verification.
• Collaborate closely with RTL, DFT, architecture, and signoff teams for seamless integration.
• Analyse and resolve congestion, timing, noise, and power-related challenges.
• Ensure delivery of highquality results that meet performance, power, and area (PPA) targets.

Key Skills & Expertise:

Mandatory Skills:

• Strong experience in PnR (Place & Route)
• Static Timing Analysis (STA) Hands-on expertise
• Proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence)

Good to Have:

• Synthesis experience
• Knowledge of low-power design techniques
• Exposure to advanced technology nodes (e.g., 7nm, 5nm, etc.)

Profile Expectations:

• Proven end-to-end Physical Design execution experience.
• Strong understanding of timing closure, implementation flows, and design methodologies.
• Ability to work independently as well as collaboratively in cross-functional teams.
• Excellent communication and debugging skills.
• Strong problemsolving mindset with attention to detail.