Lead Physical Design Engineer

ACL Digital; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

ACL Digital in Bengaluru is seeking an experienced Physical Design Engineer with over 7 years in high-performance designs. Responsibilities include handling floor-planning, routing, physical verification, and working with advanced design tools like Synopsys and Cadence.

The ideal candidate will possess strong scripting skills and the ability to work with distributed teams. This role demands excellent problem-solving abilities and attention to detail, specifically in FinFET and Dual Patterning nodes.

Qualifications

• 7+ years of professional experience in physical design, preferably with high performance designs.
• Strong experience with design tools like Synopsys and Cadence.
• Proven ability to communicate effectively and multi-task.

Responsibilities

• Handle floor-planning, physical implementation, and routing.
• Identify complex technical problems and summarize possible solutions.
• Drive flow development and scripting for design automation.

Skills

Physical design expertise

Automated synthesis

Timing-driven place and route

Communication skills

Scripting for design flow automation

Education

Bachelor's in Electronics or related

Tools

Synopsys Fusion Compiler

Design Compiler

Cadence Genus

Job description

• Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence
• Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.
• Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off
• Identify complex technical problems, break them down, summarize multiple possible solutions,
• Drive and hands-on flow development and scripting

PREFERRED EXPERIENCE

• 7+years of professional experience in physical design, preferably with high performance designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm
• Excellent physical design and timing background.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.